PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet - Page 86

• Manufacturer Part Number: PPC440GRX-NPAFFFTS
• Description: PowerPC 440GRx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

440GRx – PPC440GRx Embedded Processor
Initialization
The PPC440GRx provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GRx start-up. The actual capture instant is the nearest reference clock edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are used for strap functions only during
reset. Following reset they are used for normal functions. The signal names assigned to the pins for normal
operation are shown in parentheses following the pin number.
Note: When UART0_DCD, UART0_DSR and UART0_CTS are used functionally, the pin straps should be isolated
from the UART transceiver during reset as the transceiver may overdrive the pin straps and cause the
PPC440GRx to read incorrect straps.
The following table lists the strapping pins along with their functions and strapping options:
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GRx
sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the PowerPC 440GRx User’s Manual.
86
Table 28. Strapping Pin Assignments
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the IIC Bootstrap Controller chapter in the
PPC440GRx Embedded Processor User’s Manual
for details.
Serial device is enabled. The option being selected is
the IIC0 slave address that will respond with
strapping data.
Function
G (0xA8)
H (0xA4)
Option
A
B
C
D
E
F
(UART0_DCD)
C28
0
0
0
0
1
1
1
1
Revision 1.08 – October 15, 2007
Preliminary Data Sheet
(UART0_DSR)
Pin Strapping
C29
0
0
1
1
0
1
0
1
AMCC Proprietary
(UART0_CTS)
A29
0
1
0
1
0
0
1
1