EDD1216AASE ELPIDA [Elpida Memory], EDD1216AASE Datasheet - Page 27

• Manufacturer Part Number: EDD1216AASE
• Description: 128M bits DDR SDRAM (8M words x 16 bits)
• Manufacturer: ELPIDA [Elpida Memory]

Command Intervals
A Read command to the consecutive Read command Interval
1. Same
2. Same
3. Different
Preliminary Data Sheet E0614E20 (Ver. 2.0)
Destination row of the
consecutive read command
Bank
address
Command
Address
DQS
/CK
DQ
CK
BA
Row address State
Same
Different
Any
READ to READ Command Interval (same ROW address in the same bank)
Bank0
Active
ACT
Row
t0
ACTIVE
—
ACTIVE
IDLE
NOP
Column = A
Read
Column A
READ
t3
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
Column B
Column = B
Read
READ
t4
27
t5
Column = A
Dout
out
A0
out
A1
t6
out
B0
Column = B
Dout
out
B1
NOP
t7
out
B2
out
B3
t8
EDD1216AASE
t9
CL = 2
BL = 4
Bank0