EDD1216AJBG ELPIDA [Elpida Memory], EDD1216AJBG Datasheet

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... PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1216AJBG (8M words 16 bits) Specifications Density: 128M bits Organization 2M words 16 bits 4 banks Package: 60-ball FBGA Lead-free (RoHS compliant) Power supply: VDD, VDDQ 2.5V Data rate: 400Mbps/333Mbps/266Mbps (max.) Four internal banks for concurrent operation Interface: SSTL_2 Burst lengths (BL ...

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... Ordering Information Mask Organization Part number version (words EDD1216AJBG-5B EDD1216AJBG-5C-E EDD1216AJBG-6B-E EDD1216AJBG-7A-E EDD1216AJBG-7B-E Part Number Elpida Memory Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 12: 128M / 4-bank Organization 16: x16 Power Supply, Interface A: 2.5V, SSTL_2 Speed Grade Compatibility ...

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... CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Speed Grade Compatibility............................................................................................................................2 Electrical Specifications.................................................................................................................................4 Block Diagram .............................................................................................................................................12 Pin Function.................................................................................................................................................13 Command Operation ...................................................................................................................................15 Simplified State Diagram .............................................................................................................................22 Operation of the DDR SDRAM ....................................................................................................................23 Timing Waveforms.......................................................................................................................................42 Package Drawing ........................................................................................................................................48 Recommended Soldering Conditions..........................................................................................................49 Preliminary Data Sheet E1154E10 (Ver. 1.0) EDD1216AJBG 3 ...

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... VDDQ 0.50 VDDQ 0.51 VREF – 0.04 VREF VREF + 0.04 VREF + 0.15 — VDDQ + 0.3 –0.3 — VREF – 0.15 –0.3 — VDDQ + 0.3 0.5 VDDQ 0.2V 0.5 VDDQ 0.5 0.36 — VDDQ + 0.6 4 EDD1216AJBG Unit Note Unit Notes VDDQ VDDQ + 0. ...

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... Input ≤ VIL or ≥ VIH Input ≥ VDD – 0 Input ≤ 0.2 V -6B 330 -7A, -7B 295 5 EDD1216AJBG Notes Notes ...

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... VOUT = 1.95V — mA VOUT = 0.35V Pins min. typ. CK, /CK 1.0 — All other input pins 1.0 — CK, /CK — — All other input-only pins — — DQ, DM, DQS 2.5 — DQ, DM, DQS — — 6 EDD1216AJBG Notes max. Unit Notes ...

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... EDD1216AJBG max. Unit Notes 0.55 tCK 0.55 tCK — tCK 0 1.1 tCK ...

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... EDD1216AJBG -7B min. max. Unit Notes 7 0.45 0.55 tCK 0.45 0.55 tCK min — tCK (tCH, tCL) –0.75 0. –0.75 0. — 0.5 ...

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... Preliminary Data Sheet E1154E10 (Ver. 1.0) -6B -7A min. max. min. max 15 — 15 — (tWR/tCK)+ (tWR/tCK)+ — (tRP/tCK) (tRP/tCK) 1 — 1 — — 15.6 — 15.6 9 EDD1216AJBG -7B min. max. Unit Notes 15 — ns (tWR/tCK)+ — tCK 13 (tRP/tCK) 1 — tCK — 15.6 µs ...

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... VTT VREF VIH (AC) VREF 0.31 VIL (AC) VREF 0.31 VID (AC) 0.62 VIX (AC) VREF SLEW 1 tCK tCL tCH VIX VDD VIH VREF VIL VSS t SLEW = (VIH (AC) – VIL (AC))/ t VTT 30pF Input Waveforms and Output Load 10 EDD1216AJBG Unit V/ns VDD VREF VSS ...

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... EDD1216AJBG 7.5ns min. max. Unit 3 + BL/2 — tCK BL/2 — tCK 2 + BL/2 — tCK 2 — tCK 3 — tCK 3 — tCK 2 2 tCK 2.5 2.5 tCK 3 3 ...

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... Preliminary Data Sheet E1154E10 (Ver. 1.0) Bank 1 Row address Memory cell array buffer Bank 0 and refresh counter Sense amp. Column decoder Column address buffer and burst Data control circuit counter Latch circuit DLL CK, /CK Input & Output buffer DQ 12 EDD1216AJBG Bank 3 Bank 2 DQS DM ...

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... BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. Preliminary Data Sheet E1154E10 (Ver. 1.0) EDD1216AJBG Column address AY0 to AY8 BA1 ...

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... VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Preliminary Data Sheet E1154E10 (Ver. 1.0) 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM 14 EDD1216AJBG ...

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... L H PRE PALL REF SELF MRS EMRS EDD1216AJBG BA1 BA0 AP Address ...

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... The CKE level must be kept for 1 CK cycle at least. Preliminary Data Sheet E1154E10 (Ver. 1.0) BA1 CKE n – /CS /RAS /CAS / EDD1216AJBG Address Notes 2 2 ...

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... NOP NOP NOP BST ILLEGAL BA, CA, A10 READ/READA Starting read operation Read/READA Starting write BA, CA, A10 WRIT/WRITA operation BA, RA ACT ILLEGAL* BA, A10 PRE, PALL Pre-charge ILLEGAL 17 EDD1216AJBG Next state ldle ldle 11 — 11 — 11 — 11 — ldle — ldle ldle 11 — 11 — ...

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... NOP NOP BST ILLEGAL Starting read BA, CA, A10 READ/READA operation. Starting new write BA, CA, A10 WRIT/WRITA operation. BA, RA ACT ILLEGAL* BA, A10 PRE/PALL ILLEGAL* ILLEGAL 18 EDD1216AJBG Next state Active Active Active Active 13 — 11 — Precharging — Precharging Precharging — 14 — 14 — 11, 14 — ...

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... ILLEGAL* BA, CA, A10 WRIT/WRIT A ILLEGAL* BA, RA ACT ILLEGAL* BA, A10 PRE, PALL ILLEGAL* ILLEGAL Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL EDD1216AJBG Next state Precharging Precharging — 14 — 14 — 11, 14 — 11, 14 — — Units tCK tCK tCK tCK tCK tCK ...

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... OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table H Refer to operations in Function Truth Table L H Self-refresh L L OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 20 EDD1216AJBG Notes Idle ...

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... To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 15.6 s. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E1154E10 (Ver. 1.0) EDD1216AJBG 21 ...

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... Preliminary Data Sheet E1154E10 (Ver. 1.0) SELF REFRESH SR ENTRY SR EXIT *1 MRS REFRESH AUTO IDLE REFRESH CKE CKE_ IDLE ACTIVE POWER CKE_ DOWN CKE ROW ACTIVE BST READ WRITE READ Read WITH WITH AP AP READ READ READ WITH AP READ WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE 22 EDD1216AJBG ...

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... DLL enable DLL reset with A8 = High Power-up Sequence after CKE Goes High Preliminary Data Sheet E1154E10 (Ver. 1.0) (7) (8) PALL REF REF REF RFC RFC Disable DLL reset with A8 = Low 200 cycles (min) 23 EDD1216AJBG (9) Any MRS command 2 cycles (min.) ...

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... Reserved 0 Sequential 1 Reserved 1 Interleave Reserved 1 Reserved 2 Reserved Driver Strength 0 Normal 1 Weak 24 EDD1216AJBG Burst Length Reserved Reserved Reserved Reserved 1 1 ...

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... EDD1216AJBG Interleave ...

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... Preliminary Data Sheet E1154E10 (Ver. 1.0) tCK + tAC (ns) after the clock rising READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) 26 EDD1216AJBG t11 t9 t10 tRPST BL: Burst length ...

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... NOP tRPRE tAC,tDQSCK out0 out1 Read Operation (/CAS Latency) tn tn+0.5 tn+1 tn+2 tn+3 WRITE NOP Column tWPRE tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 Write Operation 27 EDD1216AJBG t4.5 t5 t5.5 tRPST VTT VTT out2 out3 tn+4 tn+5 in6 in7 BL: Burst length ...

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... High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 CK /CK READ Command DQS Burst Stop during a Read Operation Preliminary Data Sheet E1154E10 (Ver. 1.0) t1 t1.5 t2 t2.5 t3 t3.5 t4 BST NOP tBSTZ out0 out1 28 EDD1216AJBG t4.5 t5 t5.5 3 cycles CL: /CAS latency ...

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... Note: Internal auto-precharge starts at the timing indicated by " Preliminary Data Sheet E1154E10 (Ver. 1.0) Refer to ‘Function truth table and related tRPD 2 cycles (= BL/2) READA NOP tAC,tDQSCK out0 out1 out2 ". Read with auto-precharge NOP BL cycles in1 in2 in3 in4 ". Burst Write ( EDD1216AJBG tRP (min) ACT out3 tRP ACT ...

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... ACT command. tRCD after the ACT command, the consecutive read command can be issued NOP READ Column B out out out Column = A Column = B Read Read Column = A Dout 30 EDD1216AJBG t9 t10 t11 out out out Column = B Dout Bank0 ...

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... READ to READ Command Interval (different bank) Preliminary Data Sheet E1154E10 (Ver. 1. READ READ NOP Column A Column B Column = A Column = B Read Read Bank0 Bank3 Read Read 31 EDD1216AJBG t8 t9 t10 t11 NOP out out out out out out Bank0 Bank3 ...

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... Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. tn+1 tn+2 tn+3 tn+4 WRIT Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Column = B Write Write 32 EDD1216AJBG tn+5 tn+6 NOP Bank0 ...

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... NOP ACT Row0 Row1 Address BA DQ DQS Bank0 Bank3 Active Active WRITE to WRITE Command Interval (different bank) Preliminary Data Sheet E1154E10 (Ver. 1.0) tn tn+1 tn+2 NOP WRIT WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Bank3 Write Write 33 EDD1216AJBG tn+3 tn+4 tn+5 NOP Bank0, 3 ...

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... Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued NOP WRIT tBSTZ (= CL) out0 out1 in0 in1 OUTPUT READ to WRITE Command Interval 34 EDD1216AJBG NOP in2 in3 INPUT ...

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... Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued READ tWTR* in2 in3 WRITE to READ Command Interval 35 EDD1216AJBG NOP out0 out1 out2 OUTPUT ...

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... DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. 1 — NOP CL=3 out0 out1 out2 out3 in2 36 EDD1216AJBG High-Z High ...

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... Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. [WRITE to READ delay = 3 clock cycle] Preliminary Data Sheet E1154E10 (Ver. 1. NOP CL=3 in2 in3 out0 out1 out2 out3 READ CL=3 tWTR* in2 in3 37 EDD1216AJBG High-Z High NOP out0 out1 out2 out3 ...

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... READ DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Preliminary Data Sheet E1154E10 (Ver. 1. PRE/ NOP PALL out0 out1 out2 out3 PRE/PALL NOP out0 out1 tHZP 38 EDD1216AJBG High-Z High-Z ...

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... WRIT DM DQS DQ in0 in1 Precharge Termination in Write Cycles (same bank) ( Preliminary Data Sheet E1154E10 (Ver. 1. NOP tWPD tWR in2 in3 Last data input NOP PRE/PALL tWR in2 in3 Data masked 39 EDD1216AJBG t6 t7 PRE/PALL NOP t6 t7 NOP ...

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... ACT command, the next ACT command can be issued. ACT NOP PRE ROW: 1 Bank3 Bank0 Active Precharge tRC Bank Active to Bank Active NOP ACT BS and ROW Bank3 Active tMRD 40 EDD1216AJBG NOP ACT NOP ROW: 0 Bank0 Active NOP ...

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... Preliminary Data Sheet E1154E10 (Ver. 1. Mask Mask Write mask latency = 0 DM Control tRP* tIS tIS tIS tIH SELF Self-Refresh 41 EDD1216AJBG ≥ tSNR* 3 ≥ tSRD* 2 NOP NOP Valid NOP ...

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... Preliminary Data Sheet E1154E10 (Ver. 1.0) tIS tIH tIS tIH tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tDQSQ tQH tDSS tDSH tDQSL tDQSH tDIPW tDH tDH tDIPW 42 EDD1216AJBG VREF VREF tDQSCK tRPST tDQSQ tQH tAC tHZ tDQSQ tQH tDSS VREF tWPST VREF VREF tDIPW ...

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... Bank 0 Bank 0 Bank 0 Read Read Precharge 43 EDD1216AJBG tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST Bank0 Access = VIH or VIL ...

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... Preliminary Data Sheet E1154E10 (Ver. 1.0) tRC tRAS tDQSS tDQSL tWPST tDQSH tDS tDS tDS tDH tWR tDH 44 EDD1216AJBG tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH ...

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... Preliminary Data Sheet E1154E10 (Ver. 1. tMRD Bank 3 Bank 3 Bank 3 Read Precharge Active R:b C tRWD Bank 3 Bank 3 Active Write 45 EDD1216AJBG VIH or VIL C:b'' b’’ tWRD Bank 3 Read Read cycle =VIH or VIL ...

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... Auto-refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Preliminary Data Sheet E1154E10 (Ver. 1. High-Z tRFC Auto Bank 0 Refresh Active 46 EDD1216AJBG Bank 0 Read VIH or VIL ...

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... CK tIS CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge Self If needed refresh entry Preliminary Data Sheet E1154E10 (Ver. 1.0) tIH CKE = low High-Z tSNR tSRD Self refresh Bank 0 exit Active 47 EDD1216AJBG Bank 0 Read VIH or VIL ...

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... Package Drawing 60-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) 0 INDEX MARK Preliminary Data Sheet E1154E10 (Ver. 1.0) 8.0 ± 0.1 0 INDEX MARK 0 0.2 S 1.20 max. S 0.35 ± 0.05 B 60-φ0.45 ± 0.05 1.6 0.8 6.4 48 EDD1216AJBG Unit: mm φ0. ECA-TS2-0220-01 ...

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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD1216AJBG. Type of Surface Mount Device EDD1216AJBG: 60-ball FBGA < Lead free (Sn-Ag-Cu) > Preliminary Data Sheet E1154E10 (Ver. 1.0) EDD1216AJBG 49 ...

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... Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E1154E10 (Ver. 1.0) EDD1216AJBG 50 CME0107 ...

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... If these products/technology are sold, leased, or transferred to a third party third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E1154E10 (Ver. 1.0) EDD1216AJBG ...