EDD1216AJBG ELPIDA [Elpida Memory], EDD1216AJBG Datasheet - Page 15

• Manufacturer Part Number: EDD1216AJBG
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Command Operation
Command Truth Table
DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other
combinations than those in the table below are illegal.
Command
Ignore command
No operation
Burst stop in read command
Column address and read command
Read with auto-precharge
Column address and write command
Write with auto-precharge
Row address strobe and bank active
Precharge select bank
Precharge all bank
Refresh
Mode register set
Remark: H: VIH. L: VIL. : VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is high at the cross point of the CK rising edge and the VREF level, every input are neglected and internal
status is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data
input are neglected and internal status is held.
Burst stop in read operation [BST]
This command stops a burst read operation, which is not applicable for a burst write operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
the output buffer becomes high-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Preliminary Data Sheet E1154E10 (Ver. 1.0)
Symbol
DESL
NOP
BST
READ
READA
WRIT
WRITA
ACT
PRE
PALL
REF
SELF
MRS
EMRS
CKE
n – 1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
15
n
H
H
H
H
H
H
H
H
H
H
H
L
H
H
/CS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
/RAS /CAS /WE
H
H
H
H
H
L
L
H
H
L
L
L
L
H
H
H
L
L
L
L
H
L
H
H
L
L
H
L
L
H
H
L
L
BA1
V
V
V
V
V
V
L
L
EDD1216AJBG
V
V
V
L
H
BA0
V
V
V
AP
L
H
L
H
V
L
H
L
L
Address
V
V
V
V
V
V
V