EDD25163HBH-6ELS-F ELPIDA [Elpida Memory], EDD25163HBH-6ELS-F Datasheet
EDD25163HBH-6ELS-F
Manufacturer Part Number
EDD25163HBH-6ELS-F
Description
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
1.EDD25163HBH-6ELS-F.pdf
(60 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EDD25163HBH-6ELS-F
Manufacturer:
ELPIDA
Quantity:
17 580
Company:
Part Number:
EDD25163HBH-6ELS-F
Manufacturer:
CITIZEN
Quantity:
4 634
Specifications
Document No. E1434E30 (Ver. 3.0)
Date Published October 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Density: 256M bits
Organization: 4M words
Package: 60-ball FBGA
Power supply: VDD, VDDQ
Data rate: 333Mbps/266Mbps (max.)
1KB page size
Four internal banks for concurrent operation
Interface: LVCMOS
Burst lengths (BL): 2, 4, 8, 16
Burst type (BT):
/CAS Latency (CL): 3
Precharge: auto precharge option for each burst
access
Driver strength: normal, 1/2, 1/4, 1/8
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Operating ambient temperature range
Lead-free (RoHS compliant) and Halogen-free
Row address: A0 to A12
Column address: A0 to A8
Sequential (2, 4, 8, 16)
Interleave (2, 4, 8, 16)
Average refresh period: 7.8 s
TA = 25 C to +85 C
WTR (Wide Temperature Range), Low Power Function
EDD25163HBH-LS (16M words 16 bits)
256M bits DDR Mobile RAM
16 bits
1.7V to 1.95V
PRELIMINARY DATA SHEET
4 banks
Features
DLL is not implemented
Low power consumption
Partial Array Self-Refresh (PASR)
Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
Deep power-down mode
Double-data-rate architecture; two data transfers per
one clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Burst termination by burst stop command and
precharge command
Wide temperature range
TA = 25 C to +85 C
Elpida Memory, Inc. 2008-2009
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