EDD5108ADTA-7A ELPIDA [Elpida Memory], EDD5108ADTA-7A Datasheet - Page 32

• Manufacturer Part Number: EDD5108ADTA-7A
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

A Write command to the consecutive Read command interval: To complete the burst operation
1. Same
2. Same
3. Different
Data Sheet E0384E30 (Ver. 3.0)
Command
Destination row of the consecutive read
command
Bank
address
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
DQS
/CK
DM
DQ
CK
Row address State
Same
Different
Any
WRIT
t0
ACTIVE
—
ACTIVE
IDLE
in0
t1
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
BL/2 + 2 cycle
in1
INPUT
WRITE to READ Command Interval
tWRD (min)
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank tWRD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
NOP
in2
t2
in3
32
t3
tWTR*
READ
t4
t5
NOP
t6
out0
OUTPUT
out1
BL = 4
CL = 2
out2