EDD5108ADTA-7A ELPIDA [Elpida Memory], EDD5108ADTA-7A Datasheet - Page 38

• Manufacturer Part Number: EDD5108ADTA-7A
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Bank active command interval
1. Same
2. Different
Mode register set to Bank-active command interval
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
Data Sheet E0384E30 (Ver. 3.0)
Command
Destination row of the consecutive ACT
command
Bank
address
Address
/CK
CK
BA
Row address
Any
Any
ROW: 0
Command
ACTV
Bank0
Active
ACT
Address
/CK
CK
State
ACTIVE
ACTIVE
IDLE
tRRD
Mode Register Set
CODE
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
MRS
ROW: 1
Operation
Two successive ACT commands can be issued at tRC interval. In between two
successive ACT operations, precharge command should be executed.
Precharge the bank. tRP after the precharge command, the consecutive ACT
command can be issued.
tRRD after an ACT command, the next ACT command can be issued.
ACT
Bank3
Active
Bank Active to Bank Active
NOP
tMRD
38
NOP
tRC
BS and ROW
Precharge
ACT
Bank3
Active
Bank0
PRE
NOP
NOP
ROW: 0
ACT
Bank0
Active
NOP