ST70136B STMICROELECTRONICS [STMicroelectronics], ST70136B Datasheet
ST70136B
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ST70136B Summary of contents
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... The transmit gain is program- mable from 0 to -15dB in 1dB steps. PCI xDSL or DMT AFE USB ST70137 ST70136 ST70136 TQFP64 Full Plastic ( 1.40 mm) ORDER CODE: ST70136G LFBGA64 ( 1.7 mm) ORDER CODE: ST70136B LOOP HYBRID DRIVER TS612/TS652 LINE 1/24 ...
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VSS TEST NRESET VDD PWD SUSPEND VDDA2 VSSA2 VSAD VSRX VSSA1 RXP RXN VDDA1 VDDA3 IREF50U VDDOSC XTALO XTALI VSSOSC VSSESD VSSA6 VCOCAP IVCO VCXOUT TOP TON VDDA6 GC0 GC1 VDDA5 VSSA5 ...
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PIN LIST The following list gives the different PIN Types: AI Analog Input AIO Analog Input/Output AO Analog Ouptut DI Digital Input DIO Digital Input/Output Table 1 : Pin Assignment Pins Name TQFP LFBGA 1 B2 CTRLIN 2 ...
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ST70136 Table 1 : Pin Assignment (continued) Pins Name TQFP LFBGA 29 H7 RXN 30 G6 VDDA1 31 F5 VDDA3 32 H8 IREF50U 33 G8 V3P75V 34 G7 VSBIAS 35 F7 V375AD 36 F8 V250AD 37 F6 V125AD 38 E7 ...
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PIN DESCRIPTION 2.1 - Analog Power Supplies These pins are the positive analog power supply voltage for the DAC and the ADC section not internally connected to digital supply. In any case the voltage on these ...
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ST70136 2.11.2 - TOP This pin is the differential non-inverting tone detector input. 2.11.3 - ACTD This pin is active when tone has been detected in sleeping mode (see control register) 2.12 - CRYSTAL These pins must ...
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BLOCK DIAGRAM XTALI XTALO 62 63 INTERNAL VCXO CLOCK GENERATOR 1 TX0 16 1 TX1 15 1 TX2 14 1 TX3 13 DATA 6 CLKM INTERFACE 1 RX0 11 1 RX1 10 1 RX2 9 1 RX3 8 ...
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ST70136 4 - FUNCTIONAL DESCRIPTION 4.1 - General The ST70136 consists of the following functional blocks: – Transmit Signal Path – Receive Signal Path – Bias Voltage and Current Generation – Digital Data Interface – Control Serial Interface – Tone ...
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Figure 2 : Digital Data Interface CLKM 35.328MHz CLKWD 8.832MHz TX[0]/RX[0] a0 TX[1]/RX[ TX[2]/RX[2] TX[3]/RX[3] a3 a15 TX DATA Sign a15 RX DATA Sign 4.7 - Control Serial Interface There is a 4-pin serial digital interface (CLKWD, CTRLIN, ...
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ST70136 Figure 4 : Control Register Interface Read cycle CLKM CLKWD b15 Don’t care CTRLIN CTRLOUT R/NW 4.7.1 - AFE registers 4.7.1 Gain Control This register is located at the address “000” and is used to program the ...
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Special Features Configuration This register is located at the address “010” and is used to configure different blocks. Table 4 : Adsl Configuration (address [b2:b0]=”010”) Name Pos. Reserved 14.13 VCO-DAC 12 Other 11.4 FVCXO 3 4.7.1.4 - VCXO ...
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ST70136 4.8 - Tone Detector The tone detector is dedicated for remote activation. It operates during SUSPEND mode with PWD = 0 only. When the tone detector level received Vin over tone greater than 15 V ...
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Reset Timing Figure 6 : Reset Timing V VDD 7ms max XTAL Reset CLKM CLKWD SUSPEND 4.9.3 - Mode Management Timing Figure 7 : Mode Management Tone detector: XTAL CLKM SUSPEND PWD Stand by mode 5ms done by ...
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ST70136 5 - SPECIFICATIONS 5.1 - Absolute Maximum Ratings Supply Voltage(AVDD,DVDD) Input Voltage Input current per pin Output current per pin Storage Temperature ESD Protection General DC Specification Parameter AVDD DVDD - Active Analog Digital Oscillator - Listening Analog Digital ...
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Receive Path Specifications 70°C unless otherwise specified. The following specifications are guaranteed only when the Digital Control Interface is not active. Table 9 : Receive Path Specifications Typical specifications apply for VCC = 5.0V, ...
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ST70136 5.4 - Transmit Path Specifications 70°C unless otherwise specified. The following specifications are guaranteed only when the Digital Control Interface is not active. Table 10 : Transmit Path Specifications Typical specifications apply for VCC = ...
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Figure 8 : Tone Detector Schematic ACTD (PAD) Table 11 : Tone DetectorSpecifications Description Zin listening mode Zin normal mode Minimum differential input signal Maximum diffential input signal VCM input 5.5 - VCXO Unless otherwise noted, typical specifications apply for ...
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ST70136 70°C unless otherwise specified. Table 12 : DAC 8B Specifications Typical specifications apply for VCC = 5.0V, temperature = 27°C, nominal process and bias current. Maximum and minimum performance is with VCC ±5%, 0°C < ...
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Data and Control Timing Interface 70°C unless otherwise specified. A Figure 10 : Data and Control Timing Interface CLKM Tc CLKWD RX[0:3] TX[0:3] Ts CTRLIN CTRLOUT R/NW Symbol Description Tva Data valid time Ts ...
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ST70136 Figure 11 : Application Schematic ST70136 20/24 ...
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Figure 12 : CPE Application Synoptic & & ...
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ST70136 6 - PACKAGE MECHANICAL DATA Figure 13 : Package TQFP64 Full Plastic ( 1.40 mm Dimensions Minimum A A1 0.05 A2 1.35 B 0. ...
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PACKAGE MECHANICAL DATA Figure 14 : Package LFBGA64 ( 1.7 mm) BALL 1 IDENTIFICATION (64 PLACES) e ...
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ST70136 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...