AN666 SILABS [Silicon Laboratories], AN666 Datasheet
AN666
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AN666 Summary of contents
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... AN667: Getting Started with the Silicon Labs Precision32 IDE AN670: Integrating Silicon Labs SiM3xxxx Devices into the Keil µVision IDE Rev. 0.1 9/12 S M3U1 , ULES SiM3xxxx Address Space (RAM) Copyright © 2012 by Silicon Laboratories AN666 , XX AND DMA Channel 1 USART0 TX AN666 ...
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... AN666 4. DMA Overview The DMA consists of two modules: DMA controller (DMACTRL) and DMA peripheral crossbar (DMAXBAR). The controller provides a single access point for all 16 (SiM3U1xx and SiM3C1xx (SiM3L1xx) DMA channels and the global DMA controls. The controller is also responsible for handling arbitration between channels. The DMA peripheral crossbar assigns channels to a peripheral. When assigned and properly configured, the peripheral’ ...
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... Firmware originally sets the channel configuration descriptor; the DMA controller will modify this word as the transfer progresses, so firmware should not write to this descriptor until any active transfers for the channel are complete. Figure 3 shows the fixed memory configuration for the descriptors. Rev. 0.1 AN666 3 ...
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... AN666 ABASEPTR BASEPTR Figure 3. Channel Transfer Descriptor Memory Configuration 4 SiM3xxxx Address Space (RAM) CONFIG Channel DSTEND SRCEND CONFIG Channel DSTEND SRCEND CONFIG Channel x DSTEND SRCEND CONFIG Channel 1 DSTEND SRCEND CONFIG Channel 0 DSTEND SRCEND CONFIG Channel x DSTEND SRCEND CONFIG Channel 1 ...
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... This field is the last destination address of the DMA transfer SRCEND[31:16 SRCEND[15:0] Function DSTEND[31:16 DSTEND[15:0] Function Rev. 0.1 AN666 ...
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... AN666 Table 3. DMA0_CHx_CONFIG: Channel Configuration Bit Name Bit Name Address in Channel Transfer Descriptor: 0x0008 Bit Name 31:30 DSTAIMD Destination Address Increment Mode. This field must be set to a value that's equal to or greater than the DSTSIZE setting. 00: The destination address increments by one byte after each data transfer. ...
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... Use the Memory Scatter-Gather Alternate transfer type (primary, alternate, and scattered descriptors). 110: Use the Peripheral Scatter-Gather Primary transfer type (primary, alternate, and scattered descriptors). 111: Use the Peripheral Scatter-Gather Alternate transfer type (primary, alternate, and scattered descriptors). Function RPOWER 2 = Rev. 0.1 AN666 7 ...
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... AN666 4.2. DMA Peripheral Crossbar Peripherals are assigned to various channels, and the DMA Crossbar can be used to assign a channel to a particular peripheral. These assignments are shown in Table 4. Table 4. DMA Crossbar Channel Peripheral Assignments for SiM3U1xx Devices Peripheral AES0 RX AES0 TX AES0 XOR ...
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... Rev. 0.1 AN666 ...
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... AN666 Table 5. DMA Crossbar Channel Peripheral Assignments for SiM3C1xx Devices (Continued) Peripheral I2C0 RX I2C0 IDAC0 IDAC1 SARADC0 SARADC1 SPI0 RX SPI0 TX SPI1 RX SPI1 TX TIMER0L Overflow TIMER0H Overflow TIMER1L Overflow ...
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... Rev. 0.1 AN666 11 ...
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... AN666 Table 6. DMA Crossbar Channel Peripheral Assignments for SiM3L1xx Devices (Continued) Peripheral IDAC0 EPCA0 Capture EPCA0 Control TIMER0L Overflow TIMER0H Overflow TIMER1L Overflow TIMER1H Overflow DMAXT0 DMAXT1 Software Trigger 12 ...
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... SG 320 + SG bursts. Each data request moves one 2 NCOUNT + 1 Number of Requests ------------------------------------ - = RPOWER 2 Rev. 0.1 AN666 Address Offsets (Primary / Alternate) 16 Channels Implemented Channels Implemented 256 0 / — 256 0 / — 512 0 / 256 512 + 256 + SG 512 + 256 + SG RPOWER set of data ...
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... AN666 ABASEPTR BASEPTR Figure 4. Basic and Auto-Request Transfer Memory Configuration 4.3.2. Auto-Request Transfers Auto-request transfers use only one descriptor (primary or alternate). This transfer type only requires one data request to transfer all of the data. The controller will arbitrate as normal (every 2 interrupt will occur when the transfer completes. This transfer type is recommended for memory-to-memory transfers ...
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... DMA channel interrupt loads primary idle or performing other tasks tasks structure Primary Structure (RPOWER = 0, NCOUNT = 3) Rev. 0.1 AN666 primary structure TMD set to 0, all transfers stop until firmware configures a structure data request data request moves moves moves Idle Idle 1 word 1 word ...
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... AN666 ABASEPTR BASEPTR Figure 6. Ping-Pong Transfer Memory Configuration 16 SiM3xxxx Address Space (RAM) CONFIG Channel 0 DSTEND SRCEND CONFIG Channel 0 DSTEND SRCEND Rev. 0.1 Alternate Structures Primary Structures ...
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... Only one data request is required to execute all of the scattered transactions. The channel interrupt will occur once the last scatter-gather descriptor (programmed to a basic transfer) executes, if enabled. Arbitration occurs every RPOWER 2 of the scatter-gather descriptors. Figure 7 shows the memory scatter-gather memory configuration. NCOUNT Number of SG Structures 4 = Rev. 0.1 AN666 1 – 17 ...
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... AN666 ABASEPTR BASEPTR Figure 7. Memory and Peripheral Scatter-Gather Transfer Memory Configuration 18 SiM3xxxx Address Space (RAM) CONFIG Channel DSTEND SRCEND CONFIG Channel DSTEND SRCEND CONFIG Channel 0 DSTEND SRCEND CONFIG Channel 0 DSTEND SRCEND Rev. 0.1 (Optional) Scatter-Gather Structures Alternate Structures Primary Structures ...
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... The channel will continue in this pattern until the channel encounters a scatter-gather descriptor set to a basic or auto-request transfer. The channel interrupt will occur once the last scatter-gather descriptor (programmed to a basic transfer) executes, if enabled. Figure 7 shows the peripheral scatter-gather memory configuration. Rev. 0.1 AN666 19 ...
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... AN666 4.4. Data Requests Each DMA channel has two data requests: single and burst. Peripherals can support single requests, burst requests, or both. If configured to use a DMA channel, peripherals request data as needed using the appropriate request type. Table 8 and Table 9 lists the supported requests for the supported triggers and peripherals. ...
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... Rev. 0.1 AN666 Data Size word word word byte, half-word, or word, depending on the mode varies based on the peripheral word word byte byte, half-word, or word word byte, half-word, or ...
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... AN666 4.7. Arbitration The DMA controller is a master on the AHB bus. This allows the module to control data transfers without any interaction with the core. The channels are in a fixed priority order. Channel 0 has the highest priority, and the last implemented channel has the lowest priority ...
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... Disable data requests for the channel using the CHREQMSET register. 7. Set the DMA to fast mode using the FDMAEN bit in the SCONFIG module. 8. Enable the DMA channel using the CHENSET register. 9. (Optional) Enable the DMA channel interrupt. 10. Submit a request to start the transfer. SiM3xxxx Address Space (RAM) Rev. 0.1 AN666 23 ...
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... AN666 For memory-to-memory transfers that do not rely on a peripheral, the easiest way to initiate these transfers is to use the software request in the CHSWRCN register recommended that firmware set the channel request mask (CHREQMSET) for channels using software-initiated transfers to avoid any peripherals connected to the channel from requesting DMA transfers ...
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... Using the DMA for a Peripheral-to-Memory or Memory-to-Peripheral Transfers A peripheral-to-memory or memory-to-peripheral transfer can use the Basic DMA transfer type. USART0 RX Figure 10. Peripheral-to-Memory DMA Transfer SiM3xxxx Address Space (RAM) Figure 11. Memory-to-Peripheral DMA Transfer SiM3xxxx Address Space (RAM) DMA Channel 0 DMA Channel 1 Rev. 0.1 AN666 USART0 TX 25 ...
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... AN666 To configure a DMA channel for a peripheral-to-memory (receive) or memory-to-peripheral (transmit) data transfer: 1. Enable the AHB and APB clocks to the DMA controller. 2. Enable the DMA module (DMAEN = 1). 3. Set the address location of the channel transfer descriptors (BASEPTR). 4. Route the DMA signals from the peripheral function to a DMA channel. ...
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... Set the NCOUNT field to the total number of transfers minus this is the last action for the DMA channel, set the transfer mode to the basic type (TMD = 1). Otherwise, set the transfer mode to the ping-pong type (TMD = 3). SiM3xxxx Address Space (RAM) DMA Channel 1 Rev. 0.1 AN666 USART0 TX 27 ...
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... AN666 7. Create the alternate descriptor in memory for the desired transfer: a. Set the SRCEND field to the last address of the source data. b. Set the DSTEND field to the peripheral FIFO register. c. Set the destination and source address increment modes (DSTAIMD and SRCAIMD). For peripheral- to-memory transfers, the source should be in non-incrementing mode ...
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... If TOCOUNT reaches 0 and the internal prescaler overflows, a timeout error is declared and the DTM transitions to its DONE state. The TOERRI flag in the CONTROL register will be set and an interrupt will be generated if enabled. When it is used, the length of the timeout is equal to 256 x (TRELOAD + 1) APB clock cycles. Rev. 0.1 AN666 29 ...
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... AN666 9.1.1. State Machine Control Each of the 15 available states in a DTM block has configuration information which defines the state operation when it is active. States are set up by firmware in the RAM or flash region of the device, and when a state becomes active, its information is read into the DTM block’s STATE register. ...
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... In such cases, this is accomplished by setting the value of PRIST to the active state number. Primary State (PRIST) State Counter = 0 and Master Counter > 0 Active (State Counter = 0 or State MSTDECEN = 1) and Master Counter = 0 Secondary State (SECST) DONE Figure 13. State Transition Diagram Rev. 0.1 AN666 31 ...
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... AN666 It is also possible to instruct a state to hold off any further transfer requests until an external pin input (specified by the INHSEL field in the CONTROL register) is asserted. The DTMINH and INHSPOL fields in the state structure configure this capability for the selected inhibit pin. 9.1.4. Interrupts Within a state structure, the user can selectively enable timeout interrupts and state transition interrupts ...
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... USART0 RX DMA Channel 0 Figure 14. DTM Peripheral-to-Memory-to-Peripheral Example SiM3xxxx Address Space (RAM) DMA Channel 1 DTM Module Channel A Channel (A) (B) DONE Rev. 0.1 AN666 USART0 TX 33 ...
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... AN666 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog- intensive mixed-signal solutions ...