AN666 SILABS [Silicon Laboratories], AN666 Datasheet - Page 31

• Manufacturer Part Number: AN666
• Description: USAGE GUIDE FOR SIM3U1XX, SIM3C1XX, AND SIM3L1XX DMA AND DTM MODULES
• Manufacturer: SILABS [Silicon Laboratories]

When a given state is active, the DTM waits until both its source and destination peripherals have asserted their
DMA request signals, indicating that both are ready to transmit/receive DMA traffic. At this time, the DTM asserts
its master DMA request signal for the channel specified in the state’s DTMCHSEL field, causing the DMA engine to
perform the next task in that channel’s sequence of operation. This DMA task satisfies the source and destination
peripheral requests by moving data from the source to the destination. In general, the source and destination
peripherals will not be assigned to a DMA channel in the DMA crossbar, and all related DMA traffic will be
requested by the DTM.
9.1.3. State Transitions
Each state is associated with a number, 0 through 14. The number 15 is reserved for a DONE state, which
terminates DTM operations. The states define two possible paths for the next state, defined in the PRIST (primary
state) and SECST (secondary state) fields of the state structure. These two fields may be loaded with any valid
state value, including 15 (the DONE state). A simple representation of the DTM state transitions is shown in
Figure 13.
When a state is entered, it becomes the active state. Its information is loaded from memory into the STATE register,
and its state number will be reported in the ST field of the CONTROL register. At the same time, the state counter
(STCOUNT) will be loaded with the value in the state’s STRELOAD field. While a state is active, the DTM will
manage the data transfer between the selected source and destination peripherals, using the selected DTM
channel to request DMA operations. The operation will last as long as the DMA is still actively transferring the data.
After the transfer is complete, the state counter is decremented. If the MSTDECEN bit in the state structure is set to
1, the master counter will also be decremented.
If the master counter is non-zero and the state counter is equal to zero, the state machine will transition to the
primary state defined by PRIST. If the master counter reaches zero and either the state counter is zero or
MSTDECEN = 1, the state machine will transition to the secondary state defined by SECST. Finally, if a timeout
error occurs (TOCOUNT reaches zero) when timeouts are enabled, or if a DMA error occurs for the selected
channel, the state machine will transition to the DONE state and generate the appropriate flags. Upon exit from a
state, the value of that state is loaded into the LASTST field in the CONTROL register.
In some scenarios, a state will need to remain active until MSTCOUNT reaches zero, even if there are more than
256 requests generated. In such cases, this is accomplished by setting the value of PRIST to the active state
number.
Timeout Event
DMA Error or
Figure 13. State Transition Diagram
DONE
Active
State
Rev. 0.1
MSTDECEN = 1) and
(State Counter = 0 or
State Counter = 0 and
Master Counter = 0
Master Counter > 0
Secondary
(SECST)
(PRIST)
Primary
State
State
AN666
31