GMS81508B HYNIX [Hynix Semiconductor], GMS81508B Datasheet - Page 60

• Manufacturer Part Number: GMS81508B
• Description: HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS
• Manufacturer: HYNIX [Hynix Semiconductor]

HYUNDAI MicroElectronics
16. INTERRUPTS
The GMS815xxB interrupt circuits consist of Interrupt en-
able register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit, and Master enable flag (“I”
flag of PSW). Thirteen interrupt sources are provided. The
configuration of interrupt circuit is shown in Figure 16-2.
The External Interrupts INT0 ~ INT3 each can be transi-
tion-activated (1-to-0 or 0-to-1 transition) by selection
IEDS.
The flags that actually generate these interrupts are bit
INT0F, INT1F, INT2F and INT3F in register IRQH. When
an external interrupt is generated, the flag that generated it
is cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.
The Timer 0 ~ Timer 3 Interrupts are generated by TxIF
which is set by a match in their respective timer/counter
register. The Basic Interval Timer Interrupt is generated by
BITIF which is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADIF which is
set by finishing the analog to digital conversion.
The Watchdog timer Interrupt is generated by WDTIF
which set by a match in Watchdog timer register.
The Basic Interval Timer INterrupt is generated by BITIF
which are set by a overflow in the timer counter register.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW on page 19), the interrupt enable
DEC. 1999 Ver 1.04
IRQH
IRQL
MSB
MSB
INT0IF
ADIF
R/W
R/W
WDTIF
INT1IF
R/W
R/W
INT2IF
BITIF
R/W
R/W
INT3IF
SIOIF
R/W
R/W
Figure 16-1 Interrupt Request Flag
R/W
T0IF
-
-
T1IF
R/W
-
-
R/W
T2IF
-
-
R/W
T3IF
register (IENH, IENL), and the interrupt request flags (in
IRQH and IRQL) except Power-on reset and software
BRK interrupt. Below table shows the Interrupt priority.
Vector addresses are shown in Figure 8-6 on page 21. In-
terrupt enable registers are shown in Figure 16-3. These
registers are composed of interrupt enable flags of each in-
terrupt source and these flags determines whether an inter-
rupt will be accepted or not. When enable flag is “0”, a
corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which dis-
ables all interrupts at once.
-
-
Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
ADC Interrupt
Basic Interval Timer
Watchdog Timer
Serial Communication
LSB
LSB
Reset/Interrupt
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
Timer/Counter 0 interrupt request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
Serial Communication interrupt request flag
Basic Interval Timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
ADDRESS: 0F7
INITIAL VALUE: 0000 0000
ADDRESS: 0F5
INITIAL VALUE: 0000 ----
H
H
B
B
GMS81508B/16B/24B
Symbol
RESET
Timer 0
Timer 1
Timer 2
Timer 3
WDT
INT0
INT1
INT2
INT3
ADC
BIT
SCI
Priority
10
11
12
13
1
2
3
4
5
6
7
8
9
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