GMS81508B HYNIX [Hynix Semiconductor], GMS81508B Datasheet - Page 67

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GMS81508B

Manufacturer Part Number
GMS81508B
Description
HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
GMS81508B/16B/24B
17. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
Watchdog Timer Control
Figure 17-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
If the malfunction occurs for any cause, the watchdog tim-
64
BASIC INTERVAL TIMER
OVERFLOW
WDTR
WDTCL
W
-
7
Count source
W DTCL
Figure 17-2 WDTR: Watchdog Timer Data Register
W
6
Figure 17-1 Block Diagram of Watchdog Timer
[0E0
W
5
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
H
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
]
W
4
6-bit compare data
WDTR
Internal bus line
Counter (8-bit)
Watchdog
W
3
6
clear
W
2
6-bit compare data
comparator
W
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
1
clear
Watchdog Timer
Register
W
0
ADDRESS: 0E0
INITIAL VALUE: -011_1111
WDTON in CKCTLR [0D3
WDTIF
enable
HYUNDAI MicroElectronics
“1”
“0”
NOTE:
The WDTON bit is in register CKCTLR.
H
DEC. 1999 Ver 1.04
Watchdog Timer interrupt
B
to reset CPU
H
]

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