EM65571AGH EMC [ELAN Microelectronics Corp], EM65571AGH Datasheet - Page 75

• Manufacturer Part Number: EM65571AGH
• Description: 130COM / 128SEG 65K Color STN LCD Driver
• Manufacturer: EMC [ELAN Microelectronics Corp]

Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
Note: During a reset: {AX3, AX2, AX1, AX0} = 0H, read address: 0H
Note: During a reset: {AX7, AX6, AX5, AX4} = 0H, read address: 1H
The AX register is set to X-address of the display RAM. Data setting is divided into the
lower nibble and the upper nibble or 4-bit each.
Note: During a reset: {AY3, AY2, AY1, AY0} = 0H, read address: 2H
Note: During a reset: {AY7, AY6, AY5, AY4} = 0H, read address: 3H
Note: During a reset: {LA3, LA2, LA1, LA0}=0H, read address: 4H
Note: During a reset: {LA7, LA6, LA5, LA4}=0H, read address: 5H
8.2.1 X-address Register (AX)
8.2.2 Y-Address Register (AY)
8.2.3 Display Start Address Register (LA)
D7
D7
D7
D7
D7
D7
0
0
0
0
0
0
case of a read, a register can output to the data bus in RDB active period. The control
register and display RAM have equal access time.
The AY register is set to Y-address of the display RAM. Data setting is divided into the
lower nibble and the upper nibble or 4-bit each. Addresses 00H to 7FH corresponds to
AY7 to AY0, and (NO AND operation) 80H to FFH are reserved but the addresses for
(AY7 to AY0) = A0H, A1H are in the display RAM area for icon display.
D6
D6
D6
D6
D6
D6
0
0
0
0
1
1
D5
D5
D5
D5
D5
D5
0
0
1
1
0
0
D4
D4
D4
D4
D4
D4
0
1
0
1
0
1
AX3 AX2 AX1 AX0
AX7 AX6 AX5 AX4
AY3 AX2 AY1 AY0
AY7 AY6 AY5 AY4
LA3 LA2 LA1 LA0
LA7 LA6 LA5 LA4
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
130COM/128SEG 65K Color STN LCD Driver
CSB RS RDB WRB RE2 RE1 RE0
CSB RS RDB WRB RE2 RE1 RE0
CSB RS RDB WRB RE2 RE1 RE0
CSB RS RDB WRB RE2 RE1 RE0
CSB RS RDB WRB RE2 RE1 RE0
CSB RS RDB WRB RE2 RE1 RE0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
EM65571
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0
0
0
0
0
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0
0
0
0
0
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