GM72V66841ELT-10K HYNIX [Hynix Semiconductor], GM72V66841ELT-10K Datasheet

no-image

GM72V66841ELT-10K

Manufacturer Part Number
GM72V66841ELT-10K
Description
2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
Description
dynamic random access memory comprised of
67,108,864 memory cells and logic including
input and output circuits operating synchronously
by referring to the positive edge of the externally
provided Clock.
of 2,097,152 word by 8 bit to realize high
bandwidth with the Clock frequency up to 143
Mhz.
Features
* PC133/PC100/PC66 Compatible
* 3.3V single Power supply
* LVTTL interface
* Max Clock frequency
* 4,096 refresh cycle per 64 ms
* Two kinds of refresh operation
* Programmable burst access capability ;
* Programmable CAS latency : 2/3
* 4 Banks can operate independently or
* Burst read/burst write or burst read/single
* Input and output masking by DQM input
* One Clock of back to back read or write
* Synchronous Power down and Clock
* JEDEC Standard 54Pin 400mil TSOP II
The GM72V66841ET/ELT is a synchronous
The GM72V66841ET/ELT provides four banks
- Sequence:Sequential / Interleave
- Length
command interval
suspend capability with one Clock latency
for both entry and exit
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
143/133/125/100MHz
simultaneously
write operation capability
Package
Auto refresh / Self refresh
:1/2/4/8/FP
Pin Name
Pin Configuration
A0~A9,A11
~BA1/A12
DQ0~DQ7
BA0/A13
BA0/A13
BA1/A12
A10 / AP
VCCQ
VSSQ
A10,AP
DQM
CLK
CKE
VCC
RAS
CAS
VSSQ
VCCQ
VSSQ
VSS
VCCQ
WE
NC
CS
/CAS
/RAS
VCC
VCC
VCC
DQ0
DQ1
DQ2
DQ3
/WE
/CS
NC
NC
NC
NC
NC
A0
A1
A2
A3
SYNCHRONOUS DYNAMIC RAM
GM72V66841ET/ELT
2,097,152 WORD x 8 BIT x 4 BANK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Address input or Auto Precharge
Bank select
Data input / Data output
Data input / output Mask
V
V
Power for internal circuit
Ground for internal circuit
No Connection
CC
SS
400 mil 54 PIN TSOP II
JEDEC STANDARD
for DQ
for DQ
(TOP VIEW)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSSQ
-1-

Related parts for GM72V66841ELT-10K

GM72V66841ELT-10K Summary of contents

Page 1

Description The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. The GM72V66841ET/ELT provides four banks ...

Page 2

Block Diagram Column address counter Row decoder Memory array Bank 0 4096 row x 512 column x 8 bit Rev. 1.1/Apr. A13 Column address Row address buffer counter Row decoder Row decoder Memory array Memory ...

Page 3

Absolute Maximum Ratings Parameter Voltage on any pin relative to V Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Notes : 1. Respect Recommended DC Operating Conditions (Ta ...

Page 4

DC Characteristics ( 70C, V Parameter Symbol Operating I CC1 current Standby current in I CC2P power down Standby current in power down I CC2PS (input signal stable) Standby current in non power down I CC2N (CAS ...

Page 5

DC Characteristics ( 70C, V (Continued) Parameter Symbol Input leakage current I LI Output leakage current I LO Output high voltage V OH Output low voltage V OL Notes : 1. I depends on output load condition ...

Page 6

AC Characteristics ( 70C, V Parameter Symbol t (CL=2) System clock CK cycle time t (CL= CLK high pulse width CKH t CLK low pulse width CKL t (CL=2) Access time AC from CLK t ...

Page 7

AC Characteristics ( 70C, V (Continued) Parameter Symbol Write recovery or data-in t RWL to precharge lead time Active (a) to Active (b) t RRD command period t Refresh period REF Notes : 1. AC measurement assumes ...

Page 8

Relationship Between Frequency and Minimum Latency Parameter frequency(MHz) t (ns) CK Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write ...

Page 9

Relationship Between Frequency and Minimum Latency Parameter frequency(MHz) t (ns) CK Burst stop to (CL=2) output valid (CL=3) data hold Burst stop to (CL=2) output high (CL=3) impedance Burst stop to write data ignore Notes : ...

Page 10

Package Dimensions GM72V66841ET/ELT Series (TTP-54D) Preliminary 22.22 22.72 Max 54 1 0.80 +0.10 0.30 - 0.05 0.13 M 0.28 +/- 0.05 0.91 MAX 0.10 Dimension including the plating thickness Base material dimension Rev. 1.1/Apr. 11.76 +/- 0.20 Hitachi ...

Related keywords