K4D551638F-LC40000 Samsung, K4D551638F-LC40000 Datasheet - Page 15

• Manufacturer Part Number: K4D551638F-LC40000
• Description: No Discount To Anyone!
• Manufacturer: Samsung

K4D551638F-TC
Write Interrupted by a Read & DM
least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read
command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data
to read command (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins
before the read command is initiated will actually be written to the memory. Read command interrupting write can not be
issued at the next clock edge of that of write command.
The following function established how a Read command may interrupt a Write burst and which input data is not written
into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich imme-
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the
4. If input Write data is masked by the Read command, the DQS input is ignored by the GDDR.
* This function is only supported in 200/166MHz.
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at
CAS Latency=3
CAS Latency=3
case where the Write to Read delay is 1 clock cycle is disallowed
memory controller) in time to allow the buses to turn around before the GDDR drives them during a read operation.
diately precede the interrupting Read operation and the input data word which immediately follows the interrupting
Read operation
< Burst Length=8, CAS Latency=3 >
Command
DQS
DQ ′s
DQ ′s
DQS
CK
CK
DM
NOP
0
t
WPRES*
t
WRITE
WPRES*
5
t
DQSSmin
1
t
DQSSmax
5
Din 0
NOP
Din 0
Din 1
2
Din 1
Din 2
- 15 -
NOP
Din 2
Din 3
3
Din 3
Din 4
NOP
t
CDLR
Din 4
Din 5
t
CDLR
4
Din 5
Din 6
READ
Din 6
Din 7
5
256M GDDR SDRAM
Din 7
NOP
6
Rev 2.1 (Apr. 2005)
NOP
7
NOP
Dout 0 Dout 1
Dout 0 Dout 1
8