K4D551638F-LC40000 Samsung, K4D551638F-LC40000 Datasheet - Page 5

• Manufacturer Part Number: K4D551638F-LC40000
• Description: No Discount To Anyone!
• Manufacturer: Samsung

K4D551638F-TC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
VDDQ/VSSQ
LDQS,UDQS
DQ0 ~ DQ15
LDM,UDM
VDD/VSS
CK, CK*1
BA0, BA1
For any applications using the single ended clocking, apply V
A0 ~ A12
NC/RFU
VREF
CKE
RAS
CAS
WE
CS
Sym-
Input/Output
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
Type
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s
that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal when low. By
deactivating the clock, CKE low indicates the Power down mode or Self refresh
mode.CKE is synchronous for Power down entry and exit, and for Self refresh
entry. CKE is asynchronous for Self refresh exit, and for output disable. CKE must
be maintained high through Read and Write accesses. Input buffers, excluding CK,
CK and CKE are disbled during Power down. Input buffers, excluding CKE are dis-
abled during Self refresh. CKE is an SSTL_2 input, but will detect a LVCMOS low
level after Vdd is applied upon 1st power up. After Vref has become stable during
the power on and intialization sequence, it must be maintained for proper opera-
tion of the CKE receiver. For proper Self refresh entry and exit, Vref must be main-
tained to this input.
CS enables the command decoder when low and disabled the command decoder
when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
Latches row addresses on the positive going edge of the CK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to
the data on DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM
correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
- 5 -
REF
to CK pin.
Function
256M GDDR SDRAM
Rev 2.1 (Apr. 2005)