E28F320J5100 Intel, E28F320J5100 Datasheet - Page 12

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
V
programming,
functions
contents—block
configuration—are accessed via the CUI and
verified through the status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
program, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during program cycles.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or
program data from/to any other block.
12
PENH
A [22-0]: 64-Mbit
A [21-0]: 32-Mbit
on V
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
7FFFFF
3FFFFF
03FFFF
01FFFF
7E0000
3E0000
020000
000000
PEN
associated
enables successful block erasure,
and
erase,
Byte-Wide (x8) Mode
lock-bit
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
with
program,
configuration.
altering
Figure 5. Memory Map
memory
63
31
lock-bit
1
0
All
A [22-1]: 64-Mbit
A [21-1]: 32-Mbit
3FFFFF
1FFFFF
01FFFF
00FFFF
3F0000
1F0000
010000
000000
2.1
Depending on the application, the system designer
may choose to make the V
only when memory block erases, programs, or lock-
bit configurations are required) or hardwired to
V
practice and encourages optimization of the
processor-memory interface.
When V
altered. The CUI’s two-step block erase, byte/word
program, and lock-bit configuration command
sequences
operations even when V
program functions are disabled when V
the write lockout voltage V
The device’s block locking capability provides
additional protection from inadvertent code or data
alteration by gating erase and program operations.
3.0 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
PENH
. The device accommodates either design
PEN
Word Wide (x16) Mode
Data Protection
provide
64-Kword Block
64-Kword Block
64-Kword Block
64-Kword Block
V
PENLK
, memory contents cannot be
protection
PENH
PRELIMINARY
PEN
LKO
is applied to V
switchable (available
or when RP# is V
63
31
1
0
from
CC
unwanted
is below
PEN
0606_05
. All
IL
.