E28F320J5100 Intel, E28F320J5100 Datasheet - Page 33

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E28F320J5100

Manufacturer Part Number
E28F320J5100
Description
Manufacturer
Intel
Datasheet
High Z
Busy?
When
Yes
PRELIMINARY
No
WBS
bit 7
XSR.7 = WRITE BUFFER STATUS
XSR.6–XSR.0
ENHANCEMENTS
1 = Write buffer available
0 = Write buffer not available
Status Register Bits
=
Table 17. eXtended Status Register Definitions
RESERVED FOR FUTURE
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Reserved
bits 6–0
After a Buffer-Write command, XSR.7 = 1
indicates that a Write Buffer is available.
SR.6–SR.0 are reserved for future use and
should be masked when polling the status
register.
NOTES:
33

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