LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 10

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

Mobile Intel
1.1
1.2
10
®
Celeron
Overview
Terminology
In this document a “#” symbol following a signal name indicates that the signal is active low. This
means that when the signal is asserted (based on the name of the signal) it is in an electrical low
state. Otherwise, signals are driven in an electrical high state when they are asserted. In state
machine diagrams, a signal name in a condition indicates the condition of that signal being
asserted. If the signal name is preceded by a “!” symbol, then it indicates the condition of that
signal not being asserted. For example, the condition “!STPCLK# and HS” is equivalent to “the
active low signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS condition is true.” The
symbols “L” and “H” refer respectively to electrical low and electrical high signal levels. The
symbols “0” and “1” refer respectively to logical low and logical high signal levels. For example,
BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = “LHLH” also
refers to a hexadecimal “A.” The symbol “X” refers to a “Don’t Care” condition, where a “0” or a
“1” results in the same behavior.
Performance improved over existing mobile processors
On-die primary (L1) instruction and data caches
On-die second level (L2) cache
GTL+ system bus interface
Mobile Pentium II processor clock control
Thermal diode for measuring processor temperature
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Supports the Intel Architecture with Dynamic Execution
Supports the Intel Architecture MMX™ technology
Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance
Integrated Intel Floating Point Unit compatible with the IEEE 754 standard
4-way set associative, 32-byte line size, 1 line per sector
16-Kbyte instruction cache and 16-Kbyte write-back data cache
Cacheable range controlled by processor programmable registers
4-way set associative, 32-byte line size, 1 line per sector
Operates at full core speed
128-Kbyte, ECC protected cache data array
64-bit data bus, 100-MHz operation
Uniprocessor, two loads only (processor and I/O bridge/memory controller)
Integrated termination
Quick Start for low power, low exit latency clock “throttling”
Deep Sleep mode for even lower power dissipation
Datasheet
283654-003