LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 40

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

Mobile Intel
4.
4.1
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Table 22. BCLK Signal Quality Specifications
Table 23. PICCLK Signal Quality Specifications
®
Celeron
System Signal Simulations
Many scenarios have been simulated to generate a set of GTL+ processor system bus layout
guidelines, which are available in the Mobile Pentium
Guideline. Systems must be simulated using the IBIS model to determine if they are compliant
with this specification.
System Bus Clock (BCLK) and PICCLK AC Signal
Quality Specifications
Table 22 and Figure 15 show the signal quality for the system bus clock (BCLK) signal, and
Table 23 and Figure 15 show the signal quality for the APIC bus clock (PICCLK) signal at the
processor. BCLK and PICCLK are 2.5V clocks.
NOTES:
NOTES:
Symbol Parameter
V1
V2
V3
V4
V5
Symbol
V1
V2
V3
V4
V5
1. The clock must rise/fall monotonically between V
2. These specifications apply only when BCLK is running, see Table 12 for the DC specifications for when
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
1. The clock must rise/fall monotonically between V
2. These specifications apply only when PICCLK is running, see Table 12 for the DC specifications for when
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
BCLK is stopped. BCLK may not be above V
clock cycle.
voltage the BCLK signal can go to after passing the V
PICCLK is stopped. PICCLK may not be above V
cycle.
voltage the PICCLK signal can go to after passing the V
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
V
V
V
BCLK Rising Edge Ringback
BCLK Falling Edge Ringback
Parameter
V
V
V
PICCLK Rising Edge Ringback
PICCLK Falling Edge Ringback
IL,BCLK
IH,BCLK
IN
IL25
IH25
IN
Absolute Voltage Range
Absolute Voltage Range
Datasheet
Min
2.0
-0.7
2.0
Min Max Unit Figure
2.0
-0.7 3.5
2.0
IH,BCLK,max
Max Unit
0.5
3.5
0.5
0.7
0.7
IL,BCLK
IL25
IH25,max
and V
V
V
V
V
V
V
V
V
V
V
IH,BCLK
and V
or below V
®
IH25
or below V
III Processor GTL+ System Bus Layout
IH25
(rising) or V
Figure 15 Note 1
Figure 15 Note 1
Figure 15 Undershoot,Overshoot, Note 2
Figure 15 Absolute Value, Note 3
Figure 15 Absolute Value, Note 3
(rising) or V
Figure
Figure 15
Figure 15
Figure 15
Figure 15
Figure 15
IH,BCLK
.
.
IL,BCLK,min
IL25,min
Notes
IL,BCLK
IL25
Notes
Note 1
Note 1
Undershoot/Overshoot,
Note 2
Absolute Value, Note 3
Absolute Value, Note 3
for more than 50% of the clock
(falling) voltage limits.
for more than 50% of the
(falling) voltage limits.
283654-003