MAX11131AUI+ Maxim Integrated, MAX11131AUI+ Datasheet - Page 17

• Manufacturer Part Number: MAX11131AUI+
• Description: Analog to Digital Converters - ADC 12Bit 16 Ch 3Msps Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11131AUI+

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 72.3 dB
• Interface Type: 3-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 2162 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

Figure 4. Unipolar Transfer Function for 12-Bit Resolution
The MAX11129–MAX11132 contain a FIFO buffer that can
hold up to 16 ADC results. This allows the ADC to handle
multiple internally clocked conversions without tying up
the serial bus. If the FIFO is filled and further conversions
are requested without reading from the FIFO, the oldest
ADC results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading channel address bits. After each falling edge of
CS, the oldest available byte of data is available at DOUT.
When the FIFO is empty, DOUT is zero.
In external clock mode, the analog inputs are sampled at
the falling edge of CS. Serial clock (SCLK) is used to per-
form the conversion. The sequencer reads in the channel
to be converted from the serial data input (DIN) at each
frame. The conversion results are sent to the serial output
(DOUT) at the next frame.
The MAX11129–MAX11132 operate from an internal
oscillator, which is accurate within Q15% of the 40MHz
nominal clock rate. Request internally timed conversions
by writing the appropriate sequence to the ADC Mode
Maxim Integrated
OUTPUT CODE (hex)
FFD
FFC
FFB
FFF
FFE
004
003
002
001
000
0
1
FS = V
ZS = 0
1 LSB =
2
REF+
V
4096
3
REF+
INPUT VOLTAGE (LSB)
4
3Msps, Low-Power, Serial 12-/10-Bit,
FS -1.5 LSB
External Clock
Internal Clock
Internal FIFO
FS
Figure 5. Bipolar Transfer Function for 12-Bit Resolution
Control register
version, and shutdown sequences are initiated through
CNVST and are performed automatically using the inter-
nal oscillator. Results are added to the internal FIFO.
With CS high, initiate a scan by setting CNVST low for
at least 5ns before pulling it high
MAX11129–MAX11132 wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the serial
interface. EOC stays low until CS or CNVST is pulled low
again. Do not initiate a second CNVST before EOC goes
low; otherwise, the FIFO may become corrupted.
Alternatively, set SWCNV to 1 in the ADC Mode Control
register to initiate conversions with CS rising edge
instead of cycling CNVST
CS must be held low for 17 clock cycles to guarantee
that the device interprets the SWCNV setting. A delay
is initiated at the rising edge of CS and the conversion
is started when the delay times out. Upon completing
the conversion, this bit is reset to 0
soft reset when changing from internal to external clock
mode: RESET[1:0] = 10.
OUTPUT CODE (hex)
MAX11129–MAX11132
7FF
7FE
001
000
FFF
FFE
801
800
8-/16-Channel ADCs
-FS
+FS =
ZS = 0
-FS =
1 LSB =
(Table
-FS +0.5 LSB
V
-V
REF+
2
2
V
REF+
4096
REF+
2). The wake-up, acquisition, con-
INPUT VOLTAGE (LSB)
(Table
0
2). For proper operation,
+FS -1.5 LSB
(Figure
(Figure
6). Then, the
7). Apply a
+FS
17