MAX11131AUI+ Maxim Integrated, MAX11131AUI+ Datasheet - Page 31

• Manufacturer Part Number: MAX11131AUI+
• Description: Analog to Digital Converters - ADC 12Bit 16 Ch 3Msps Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11131AUI+

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 72.3 dB
• Interface Type: 3-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 2162 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

Figure 10. SampleSet Timing Diagram
1) Configure the ADC (set the MSB on DIN to 1).
2) Program ADC mode control (set the MSB on DIN to 0)
See
Maxim Integrated
to begin the conversion process or to control power
management features.
• If ADC mode control is written during a conversion
• If configuration data (MSB on DIN is a 1) is written
DOUT
SCLK
Figure 11
DIN
CS
sequence, the ADC finishes the present conver-
sion and at the next falling edge of CS initiates its
new instruction.
during a conversion sequence, the ADC finishes
the present conversion in the existing scan mode.
However, data on DOUT is not valid in following
frames until a new ADC mode control instruction
is coded.
Programming Sequence Flow Chart
1
for programming sequence.
Applications Information
WRITE SampleSet REGISTER
DEFINE SEQ_LENGTH
How to Program Modes
3Msps, Low-Power, Serial 12-/10-Bit,
16
1
ENTRY 1
RISING EDGE DEPENDS IN SEQ_LENGTH
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
OVDD, and REF affects the ADC’s perfor mance. Bypass
the V
bypass capacitors. Minimize capacitor lead and trace
lengths for best supply-noise rejection.
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
and stays within a given error band centered on the
resulting steady-state amplifier output level. The ADC
input sampling capacitor charges during the sampling
cycle, referred to as the acquisition period. During this
acquisition period, the settling time is affected by the
input resistance and the input sampling capacitance.
This error can be estimated by looking at the settling
of an RC time constant using the input capacitance
and the source impedance over the acquisition time
period.
MAX4430, offering a settling time of 37ns at 16-bit reso-
lution, is an excellent choice for this application. See the
THD vs. Input Resistance
Characteristics.
TIME BETWEEN CS FALLING AND
ENTRY 2
LOAD SampleSet PATTERN
MAX11129–MAX11132
DD
Figure 13
, OVDD, and REF to ground with 0.1FF and 10FF
8-/16-Channel ADCs
Layout, Grounding, and Bypassing
ENTRY N = (SEQ_LENGTH)
shows a typical application circuit. The
Choosing an Input Amplifier
graph in the Typical Operating
OR CONTINUE WITH ADDITIONAL
WRITE ADC MODE CONTROL
CONFIGURATION SETTINGS
1
DD
31
,