MAX11131AUI+ Maxim Integrated, MAX11131AUI+ Datasheet - Page 22

• Manufacturer Part Number: MAX11131AUI+
• Description: Analog to Digital Converters - ADC 12Bit 16 Ch 3Msps Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11131AUI+

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: 72.3 dB
• Interface Type: 3-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 2162 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

Table 2. ADC Mode Control Register (continued)
Table 3. ADC Scan Control
Maxim Integrated
SCAN3
BIT NAME
CHAN_ID
0
0
0
0
PM[1:0]
SWCNV
—
SCAN2
0
0
0
0
BIT
4:3
SCAN1
2
1
0
0
0
1
1
DEFAULT
STATE
SCAN0
00
0
0
0
0
1
0
1
3Msps, Low-Power, Serial 12-/10-Bit,
MODE NAME
Power Management Modes (Table 5). In external clock mode, PM[1:0] selects
between normal mode and various power-down modes of operation.
External Clock Mode. Channel address is always present in internal clock mode.
Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by
a 12-bit conversion result led by the MSB.
Set to 1 to initiate conversions with the rising edge of CS instead of cycling CNVST
(internal clock mode only).
This bit is used for the internal clock mode only and must be reasserted in the ADC
mode control, if another conversion is desired.
Unused
Standard_Int
Manual
Repeat
N/A
Continue to operate in the previously selected mode. Ignore data
on bits [10:0]. This feature is provided so that DIN can be held low
when no changes are required in the ADC Mode Control register.
Bits [6:3, 1] can be still written without changing the scan mode
properties.
The next channel to be selected is identified in each SPI frame. The
conversion results are sent out in the next frame.
Clock mode: External clock only
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: No
Scans channel N repeatedly. The FIFO stores 4, 8, 12, or 16
conversion results for channel N.
Clock mode: Internal clock only
Channel scan/sequence: Single channel per frame
Channel selection: See Table 4, CHSEL[3:0]
Averaging: Yes
Scans channels 0 through N. The FIFO stores N conversion results.
Clock mode: Internal clock
Channel scan/sequence: N channels in ascending order
Channel selection: See Table 4, CHSEL[3:0] determines channel N
Averaging: Yes
MAX11129–MAX11132
8-/16-Channel ADCs
FUNCTION
FUNCTION
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