530GC24M5760DG Silicon Labs, 530GC24M5760DG Datasheet - Page 11

• Manufacturer Part Number: 530GC24M5760DG
• Description: Standard Clock Oscillators SINGLE XO 6 PIN 0.3PS RS JTR
• Manufacturer: Silicon Labs

Specifications of 530GC24M5760DG

• Product Category: Standard Clock Oscillators
• Rohs: yes
• Product: XO
• Package / Case: 7 mm x 5 mm
• Frequency: 24.576 MHz
• Frequency Stability: 20 PPM
• Supply Voltage: 2.5 V
• Load Capacitance: 15 pF
• Termination Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Maximum Operating Temperature: + 85 C
• Output Format: CMOS
• Dimensions: 5 mm W x 7 mm L
• Mounting Style: SMD/SMT

D
Revision 0.4 to Revision 0.5
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Revision 0.5 to Revision 1.0
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Revision 1.0 to Revision 1.1
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OCUMENT
Updated Table 1, “Recommended Operating
Conditions,” on page 2.
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Updated Table 4, “CLK± Output Phase Jitter,” on
page 4 to include maximum rms jitter generation
specifications and updated typical rms jitter
specifications.
Added Table 6, “CLK± Output Phase Noise
(Typical),” on page 4.
Added Output Enable active polarity as an option in
Figure 1, “Part Number Convention,” on page 7.
Updated Note 3 in Table 1, “Recommended
Operating Conditions,” on page 2.
Updated Figure 1, “Part Number Convention,” on
page 7.
Updated Table 1, “Recommended Operating
Conditions,” on page 2.
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Updated Table 2, “CLK± Output Frequency
Characteristics,” on page 2.
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Updated Table 3, “CLK± Output Levels and
Symmetry,” on page 3.
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Updated Table 4, “CLK± Output Phase Jitter,” on
page 4.
Updated Table 5, “CLK± Output Period Jitter,” on
page 4.
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Updated Table 9, “Absolute Maximum Ratings
page 5 to reflect the soldering temperature time at
260 ºC is 20–40 sec per JEDEC J-STD-020C.
Updated 3. "Ordering Information" on page 7.
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Added 5. "Si530/Si531 Mark Specification" on page
9.
Added maximum supply current specifications.
Specified relationship between temperature at startup
Device maintains stable operation over –40 to +85 ºC
operating temperature range.
Supply current specifications updated for revision D.
Added specification for ±20 ppm lifetime stability
(±7 ppm temperature stability) XO.
Updated LVDS differential peak-peak swing
specifications.
Revised period jitter specifications.
Changed ordering instructions to revision D.
and operation temperature.
C
HANGE
L
IST
1
,” on
Rev. 1.3
Revision 1.1 to Revision 1.2
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Revision 1.2 to Revision 1.3
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Updated 2.5 V/3.3 V and 1.8 V CML output level
specifications for Table 3 on page 3.
Added footnotes clarifying max offset frequency test
conditions for Table 4 on page 4.
Added CMOS phase jitter specs to Table 4 on
page 4.
Removed the words "Differential Modes:
LVPECL/LVDS/CML" in the footnote referring to
AN256 in Table 4 on page 4.
Separated 1.8 V, 2.5 V/3.3 V supply voltage
specifications in Table 9 on page 5.
Updated and clarified Table 9 on page 5 to include
the "Moisture Sensitivity Level" and "Contact Pads"
rows.
Updated Figure 3 on page 9 and Table 13 on page 9
to reflect specific marking information. Previously,
Figure 3 was generic.
Added Table 8, “Thermal Characteristics,” on
page 5.
Si530/531
11