S9S12G96F0VLF Freescale Semiconductor, S9S12G96F0VLF Datasheet - Page 348

• Manufacturer Part Number: S9S12G96F0VLF
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

S12S Debug Module (S12SDBGV2)
event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
This however violates the S12SDBGV1 specification, which states that a match leading to final state
always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel
number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on
simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state
then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG
would break on a simultaneous M0/M2.
350
SCR3=0001
SCR3=1110
SCR1=0100
SCR1=0110
Figure 8-33. Scenario 4b (with 2 comparators)
MC9S12G Family Reference Manual, Rev.1.23
Figure 8-32. Scenario 4a
M1
M2
State1
State1
State 3
State 3
M2
M0
M0
M0
M1
M2
M1
M2
Final State
Final State
State2
State2
M0
M01
SCR2=0011
SCR2=1100
M1 disabled in
range mode
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