S9S12G96F0VLF Freescale Semiconductor, S9S12G96F0VLF Datasheet - Page 403

• Manufacturer Part Number: S9S12G96F0VLF
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

10.4
10.4.1
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to f
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK
can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]
bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock
by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,
3, 4, 5, 6,... to 32 to generate the PLLCLK.
Freescale Semiconductor
.
If oscillator is enabled (OSCE=1)
If oscillator is disabled (OSCE=0)
f VCO
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
Functional Description
=
Phase Locked Loop with Internal Filter (PLL)
2 f REF
×
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
×
(
SYNDIV
+
MC9S12G Family Reference Manual, Rev.1.23
f PLL
f PLL
f bus
1
)
=
=
=
f REF
f REF
f PLL
------------ -
---------------------------------------- -
(
f VCO
---------------
POSTDIV
2
4
=
=
f VCO
------------------------------------
(
f IRC1M
REFDIV
NOTE
f OSC
+
1
)
+
1
S12 Clock, Reset and Power Management Unit (S12CPMU)
)
IRC1M_TRIM
=1MHz.
405