LCMXO640E-5FN256C

Manufacturer Part NumberLCMXO640E-5FN256C
DescriptionCPLD - Complex Programmable Logic Devices Use LCMXO640E-5FTN25
ManufacturerLattice
LCMXO640E-5FN256C datasheet
 

Specifications of LCMXO640E-5FN256C

RohsyesMemory TypeSRAM
Number Of Macrocells320Maximum Operating Frequency600 MHz
Delay Time3.5 nsNumber Of Programmable I/os159
Operating Supply Voltage1.2 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature0 CPackage / CaseFPBGA
Mounting StyleSMD/SMTFactory Pack Quantity450
Supply Current14 mASupply Voltage - Max1.26 V
Supply Voltage - Min1.14 V  
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Lattice Semiconductor
PIO Groups
On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells
and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO
groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective
sysIO buffers and PADs.
On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O
pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.
The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger
devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these
devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI
support.
Figure 2-15. Group of Four Programmable I/O Cells
Four PIOs
Figure 2-16. Group ofþSix Programmable I/O Cells
Six PIOs
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
MachXO Family Data Sheet
This structure is used on the
left and right of MachXO devices
PADA "T"
PIO A
PIO B
PADB "C"
PIO C
PADC "T"
PIO D
PADD "C"
This structure is used on the top
and bottom of MachXO devices
PADA "T"
PIO A
PIO B
PADB "C"
PIO C
PADC "T"
PIO D
PADD "C"
PIO E
PADE "T"
PIO F
PADF "C"
2-14
Architecture