S9S12GA240F0MLL Freescale Semiconductor, S9S12GA240F0MLL Datasheet - Page 671

• Manufacturer Part Number: S9S12GA240F0MLL
• Description: 16-bit Microcontrollers - MCU 16BIT 240KB FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GA240F0MLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 240 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

Freescale Semiconductor
SCISWAI
LOOPS
WAKE
RSRC
Field
ILT
PE
PT
M
7
6
5
4
3
2
1
0
LOOPS
Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI
and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must
be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit.
SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
0 SCI enabled in wait mode
1 SCI disabled in wait mode
Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register
input. See
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.
0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the
most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
0 Idle character bit count begins after start bit
1 Idle character bit count begins after stop bit
Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the
most significant bit position.
0 Parity function disabled
1 Parity function enabled
Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even
parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
0 Even parity
1 Odd parity
0
1
1
Table
RSRC
x
0
1
20-5.
Normal operation
Loop mode with transmitter output internally connected to receiver input
Single-wire mode with TXD pin connected to receiver input
MC9S12G Family Reference Manual, Rev.1.23
Table 20-4. SCICR1 Field Descriptions
Table 20-5. Loop Functions
Description
Function
Serial Communication Interface (S12SCIV5)
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