S9S12GN32F0MFT Freescale Semiconductor, S9S12GN32F0MFT Datasheet - Page 649

• Manufacturer Part Number: S9S12GN32F0MFT
• Description: 16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0MFT

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2048 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

19.3.2.10 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
The counter can be read at any time without affecting the count or the operation of the PWM channel. In
left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned
output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the effective period (see
Section 19.4.2.5, “Left Aligned Outputs”
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the
PWMCNTx register. For more detailed information on the operation of the counters, see
“PWM Timer
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
1
Read: Anytime
Write: Anytime (any value written causes PWM counter to be reset to $00).
19.3.2.11 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
Freescale Semiconductor
Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3
Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
•
W
R
The effective period ends
Bit 7
0
0
7
Counters”.
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
Figure 19-12. PWM Channel Counter Registers (PWMCNTx)
0
0
6
6
MC9S12G Family Reference Manual, Rev.1.23
0
0
5
5
and
Section 19.4.2.6, “Center Aligned Outputs”
NOTE
0
0
4
4
0
0
3
3
Pulse-Width Modulator (S12PWM8B8CV2)
0
0
2
2
0
0
1
1
Section 19.4.2.4,
for more
Bit 0
0
0
0
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