S9S12G64F0MLH Freescale Semiconductor, S9S12G64F0MLH Datasheet - Page 1209

• Manufacturer Part Number: S9S12G64F0MLH
• Description: 16-bit Microcontrollers - MCU S12 Core,64k Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
1
2
A.4.2
Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC.
A further factor is that port AD pins that are configured as output drivers switching.
A.4.2.1
The accuracy is reduced if the differential reference voltage is less than 3.13V when using the ATD in the
3.3V range or if the differential reference voltage is less than 4.5V when using the ATD in the 5V range.
A.4.2.2
Port AD output drivers switching can adversely affect the ADC accuracy whilst converting the analog
voltage on other port AD pins because the output drivers are supplied from the VDDA/VSSA ADC supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
is recommended to configure port AD pins as outputs only for low frequency, low load outputs. The impact
on ADC accuracy is load dependent and not specified. The values specified are valid under condition that
no port AD output drivers switch during conversion.
A.4.2.3
Due to the input pin leakage current as specified in conjunction with the source resistance there will be a
voltage drop from the signal source to the ADC input. The maximum source resistance R
Freescale Semiconductor
Supply voltage 3.13 V < V
Num C
see
The minimum time assumes a sample time of 4 ADC clock cycles. The maximum time assumes a sample time of 24 ADC
clock cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ADC clock cycles.
1
2
3
4
5
8
Table A-4
D Reference potential
D Voltage difference V
D Voltage difference V
C Differential reference voltage
C ADC Clock Frequency (derived from bus clock via the
D
prescaler bus)
ADC Conversion Period
12 bit resolution:
10 bit resolution:
8 bit resolution:
Factors Influencing Accuracy
Low
High
Differential Reference Voltage
Port AD Output Drivers Switching
Source Resistance
DDA
< 5.5 V, -40
DDX
SSX
2
to V
to V
Rating
Table A-19. ADC Operating Characteristics
MC9S12G Family Reference Manual, Rev.1.23
SSA
DDA
o
C < T
J
< T
Jmax
1
N
N
V
Symbol
N
f
∆
∆
ATDCLk
RH
CONV12
CONV10
CONV8
V
V
VDDX
VSSX
RH
RL
-V
RL
V
–2.35
V
–0.1
3.13
0.25
DDA
Min
20
19
17
SSA
/2
Typ
5.0
—
—
0
0
Electrical Characteristics
S
specifies results
V
V
Max
DDA
0.1
0.1
5.5
8.0
42
41
39
DDA
/2
Cycles
clock
MHz
ADC
Unit
V
V
V
V
V
1211