SPC5646CF0MLU1 Freescale Semiconductor, SPC5646CF0MLU1 Datasheet - Page 8

• Manufacturer Part Number: SPC5646CF0MLU1
• Description: 32-bit Microcontrollers - MCU 3M FLASH,25 6K RAM,120MHz
• Manufacturer: Freescale Semiconductor

Specifications of SPC5646CF0MLU1

• Rohs: yes
• Core: e200
• Processor Series: MPC5646C
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 3 MB
• Data Ram Size: 256 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 0.3 V to 6.2 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-176
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 33
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 147
• Number Of Timers: 32
• Program Memory Type: Flash
• Supply Voltage - Max: 6.2 V
• Supply Voltage - Min: 0.3 V

Block diagram
8
LinFlexD (Local Interconnect
Network Flexible with DMA
support)
Memory protection unit (MPU)
Clock generation module
(MC_CGM)
Power control unit (MC_PCU)
Reset generation module
(MC_RGM)
Mode entry module (MC_ME)
Non-Maskable Interrupt (NMI)
Nexus Development Interface
(NDI)
Periodic interrupt timer/ Real Time
Interrupt Timer (PIT_RTI)
Real-time counter (RTC/API)
Static random-access memory
(SRAM)
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
System status and configuration
module (SSCM)
System timer module (STM)
Semaphores
Wake Unit (WKPU)
Block
Table 2. MPC5646C series block summary (continued)
MPC5646C Microcontroller DataSheet, Rev. 5.1
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Provides hardware access control for all memory references generated in a
device
Provides logic and control required for the generation of system and peripheral
clocks
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Centralizes reset sources and manages the device reset sequence of the device
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Handles external events that must produce an immediate response, such as
power down detection
Provides real-time development capabilities for e200z0h and e200z4d core
processor
Produces periodic interrupts and triggers
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode). Supports autonomous
periodic interrupt (API) function to generate a periodic wakeup request to exit a
low power mode or an interrupt request
Provides storage for program code, constants, and variables
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AutoSAR and operating
system tasks
Provides the hardware support needed in multi-core systems for sharing
resources and provides a simple mechanism to achieve lock/unlock operations
via a single write access.
Supports external sources that can generate interrupts or wakeup events, of
which can cause non-maskable interrupt requests or wakeup events.
Function
Freescale