SPC5646CF0MLU1 Freescale Semiconductor, SPC5646CF0MLU1 Datasheet - Page 81

• Manufacturer Part Number: SPC5646CF0MLU1
• Description: 32-bit Microcontrollers - MCU 3M FLASH,25 6K RAM,120MHz
• Manufacturer: Freescale Semiconductor

Specifications of SPC5646CF0MLU1

• Rohs: yes
• Core: e200
• Processor Series: MPC5646C
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 3 MB
• Data Ram Size: 256 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 0.3 V to 6.2 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-176
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 33
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 147
• Number Of Timers: 32
• Program Memory Type: Flash
• Supply Voltage - Max: 6.2 V
• Supply Voltage - Min: 0.3 V

4.18
MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are not TTL compatible. They follow
the CMOS electrical characteristics.
4.18.1
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency in 2:1 mode and two times
the RX_CLK frequency in 1:1 mode.
4.18.2
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency in 2:1 mode and two times
the TX_CLK frequency in 1:1 mode.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the MPC5646C Reference Manual for details of this option and how to
enable it.
Freescale
9
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Fast Ethernet Controller
Spec
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
M1
M2
M3
M4
RXD[3:0] (inputs)
RX_CLK (input)
RX_DV
RX_ER
RXD[3:0], RX_DV,
RX_ER to RX_CLK
setup
RX_CLK to
RXD[3:0], RX_DV,
RX_ER hold
RX_CLK pulse width
high
RX_CLK pulse width
low
Characteristic
Figure 20. MII receive signal timing diagram
MPC5646C Microcontroller DataSheet, Rev. 5.1
Table 44. MII Receive Signal Timing
M1
M2
35%
35%
Min
5
5
M3
65%
65%
Max
M4
—
—
Electrical Characteristics
RX_CLK period
RX_CLK period
Unit
ns
ns
81