DS1852B-000/C Maxim Integrated, DS1852B-000/C Datasheet - Page 11

• Manufacturer Part Number: DS1852B-000/C
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of DS1852B-000/C

• Part # Aliases: 90-1852B-00C

DS1852
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves”. A master device that generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions must control the bus. The DS1852 operates as a slave
on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The
following I/O terminals control the 2-wire serial port: SDA, SCL, and ASEL. Timing diagrams for the
2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications.
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two
types of data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1852 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an ‘acknowledge’ after
the byte has been received. The master device must generate an extra clock pulse, which is associated
with this acknowledge bit.
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