DS1852B-000/C Maxim Integrated, DS1852B-000/C Datasheet - Page 8

• Manufacturer Part Number: DS1852B-000/C
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of DS1852B-000/C

• Part # Aliases: 90-1852B-00C

DS1852
DIGITAL INPUTS
The four digital inputs (D
, RS
, F
, and L
) can be read through the 2-wire bus. The logic levels at
in
in
in
in
these inputs are mirrored in the “logic states” byte (6Eh) in Table 00h.
2-WIRE OPERATION
Clock and Data Transitions
The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only
change during SCL low time periods. Data changes during SCL high periods will indicate a start or stop
conditions depending on the conditions discussed below. See Figure 2 for further details.
Start Condition
A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command. See Figure 2 for further details.
Stop Condition
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command places the DS1852 into a low-power mode. See Figure 2 for further details.
Acknowledge Bit
All address bytes and data bytes are transmitted through a serial protocol. The DS1852 pulls SDA low
during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode
The DS1852 features a low-power mode that is automatically enabled after power-on, after a stop
command, and after the completion of all internal operations.
2-Wire Interface Reset
After any interruption in protocol, power loss, or system reset, the following steps reset the DS1852:
1) Clock up to nine cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a start condition while SDA is high.
Device Addressing
The DS1852 must receive an 8-bit device address word following a start condition to enable a specific
device for a read or write operation. The address word is clocked into the DS1852 MSB to LSB. The
address word defaults to A0h then the R/W (READ/WRITE) bit when ASEL is a logic zero. If the R/W
bit is high, a read operation is initiated. If R/W is low, a write operation is initiated. The device address
is changed to the internal chip address (Table 03h address D0h) when ASEL is logic one. The default
internal chip address from the factory is A2h.
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