DS1852B-000/C Maxim Integrated, DS1852B-000/C Datasheet - Page 14

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DS1852B-000/C

Manufacturer Part Number
DS1852B-000/C
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS1852B-000/C

Part # Aliases
90-1852B-00C
MEMORY MAP
Memory access to the DS1852 is through the 2-wire interface. See the 2-WIRE OPERATION section.
The memory within the DS1852 is organized into multiple tables. The lower 128 bytes of memory are
common to all tables, the upper 128 bytes are addressed according to the table select byte at 7Fh. Valid
values of the table address byte are 00h to 03h, to access Tables 00h through 03h.
The following tables detail the memory contents. Where descriptions are underlined an expanded table
indicates the function of individual bits within the byte. The reserved memory locations should not be
used even though R/W access may be possible.
Not all memory is EEPROM; RAM cells are shaded within the tables, and denoted beneath.
00h
80h
*For permission details of this memory block refer to following table.
W - Level 2*
Tables 00h –
No Physical
Table 00h
128 Bytes
128 bytes
Memory
Lower
R- All
Upper
03h
7Fh
FF
80h
R/W - Level 1
Table 01h
128 Bytes
Upper
FF
80h
14 of 26
R/W - Level 2
Table 02h
128 Bytes
Upper
FF
80h
R/W - Level 2
Table 03h
128 Bytes
Upper
FF

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