LPC1317FBD64,551 NXP Semiconductors, LPC1317FBD64,551 Datasheet
LPC1317FBD64,551
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LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller flash SRAM; USB device; USART; EEPROM Rev. 3 — 20 September 2012 1. General description The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a ...
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... NXP Semiconductors Debug options: Standard JTAG test interface for BSDL. Serial Wire Debug. Support for ETM ARM Cortex-M3 debug time stamping. Digital peripherals: General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins support programmable glitch filter. ...
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... NXP Semiconductors Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity. Processor wake-up from Deep power-down mode using one special function pin. Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. ...
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... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash [kB] LPC1345FHN33 32 LPC1345FBD48 32 LPC1346FHN33 48 LPC1346FBD48 48 LPC1347FHN33 64 LPC1347FBD48 64 LPC1347FBD64 64 LPC1315FHN33 32 LPC1315FBD48 32 LPC1316FHN33 48 LPC1316FBD48 48 LPC1317FHN33 64 LPC1317FBD48 64 LPC1317FBD64 64 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 SRAM [kB] EEPROM [kB] SRAM0 USB SRAM1 SRAM ...
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... NXP Semiconductors 5. Block diagram LPC1315/16/17 LPC1345/46/47 system bus HIGH-SPEED GPIO ports 0/1 GPIO RXD TXD (1) (1) DCD , DSR , RI SMARTCARD INTERFACE CTS, RTS, DTR SCLK CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 (2) CT16B0_CAP[1:0] CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 (2) CT16B1_CAP[1:0] CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 (2) CT32B0_CAP[1:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration HVQFN33 package (LPC1315/16/ USB) LPC1315_16_17_45_46_47 Product data sheet terminal 1 index area LPC1315FHN33 XTALIN 4 LPC1316FHN33 5 XTALOUT LPC1317FHN33 Transparent top view All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO1_19/DTR/SSEL1 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 3. Pin configuration HVQFN33 package (LPC1345/46/47 - with USB) LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 terminal 1 index area 1 2 RESET/PIO0_0 3 LPC1345FHN33 XTALIN 4 LPC1346FHN33 XTALOUT 5 LPC1347FHN33 Transparent top view All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO1_14/DSR/CT16B0_MAT1/RXD PIO1_22/RI/MOSI1 SWDIO/PIO0_15/AD4/CT32B1_MAT2 PIO0_16/AD5/CT32B1_MAT3/WAKEUP PIO0_23/AD7 PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_17/RTS/CT32B0_CAP0/SCLK PIO0_18/RXD/CT32B0_MAT0 PIO0_19/TXD/CT32B0_MAT1 PIO1_16/RI/CT16B0_CAP0 Fig 4. Pin configuration LQFP48 package (LPC1315/16/ USB) LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/ LPC1315FBD48 SS LPC1316FBD48 42 LPC1317FBD48 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO1_14/DSR/CT16B0_MAT1/RXD PIO1_22/RI/MOSI1 SWDIO/PIO0_15/AD4/CT32B1_MAT2 PIO0_16/AD5/CT32B1_MAT3/WAKEUP PIO0_23/AD7 PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_17/RTS/CT32B0_CAP0/SCLK PIO0_18/RXD/CT32B0_MAT0 PIO0_19/TXD/CT32B0_MAT1 PIO1_16/RI/CT16B0_CAP0 Fig 5. Pin configuration LQFP48 package (LPC1345/46/47 - with USB) LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/ LPC1345FBD48 42 LPC1346FBD48 LPC1347FBD48 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO1_14 PIO1_3 PIO1_22 SWDIO/PIO0_15 PIO0_16 SSA PIO0_23 PIO1_15 DDA PIO0_17 PIO0_18 PIO0_19 PIO1_16 VREFP See Table 3 for the full pin name. Fig 6. Pin configuration LQFP64 package (LPC1315/16/ USB) LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/ ...
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... NXP Semiconductors PIO1_14 PIO1_3 PIO1_22 SWDIO/PIO0_15 PIO0_16 SSA PIO0_23 PIO1_15 DDA PIO0_17 PIO0_18 PIO0_19 PIO1_16 VREFP Fig 7. Pin configuration LQFP64 package (LPC1345/46/47 - with USB) LPC1315_16_17_45_46_47 Product data sheet LPC1345/46/ All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description (LPC1315/16/ USB) Symbol RESET/PIO0_0 4 PIO0_1/CLKOUT/ 5 CT32B0_MAT2 PIO0_2/SSEL0/ 13 CT16B0_CAP0 PIO0_3 19 PIO0_4/SCL 20 PIO0_5/SDA 21 PIO0_6/R/ 29 SCK0 PIO0_7/CTS 30 PIO0_8/MISO0/ 36 CT16B0_MAT0 PIO0_9/MOSI0/ 37 CT16B0_MAT1/ SWO LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ RESET — External reset input with 20 ns glitch filter. A ...
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... NXP Semiconductors Table 3. Pin description (LPC1315/16/ USB) Symbol SWCLK/PIO0_10/SCK0/ 38 CT16B0_MAT2 TDI/PIO0_11/AD0/ 42 CT32B0_MAT3 TMS/PIO0_12/AD1/ 44 CT32B1_CAP0 TDO/PIO0_13/AD2/ 45 CT32B1_MAT0 TRST/PIO0_14/AD3/ 46 CT32B1_MAT1 SWDIO/PIO0_15/AD4/ 52 CT32B1_MAT2 PIO0_16/AD5/ 53 CT32B1_MAT3/WAKEUP PIO0_17/RTS/ 60 CT32B0_CAP0/SCLK LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ SWCLK — Serial wire clock and test clock TCK for JTAG interface ...
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... NXP Semiconductors Table 3. Pin description (LPC1315/16/ USB) Symbol PIO0_18/RXD/ 61 CT32B0_MAT0 PIO0_19/TXD/ 62 CT32B0_MAT1 PIO0_20/CT16B1_CAP0 11 PIO0_21/CT16B1_MAT0/ 22 MOSI1 PIO0_22/AD6/ 40 CT16B1_MAT1/MISO1 PIO0_23/AD7 56 PIO1_0/CT32B1_MAT0 1 PIO1_1/CT32B1_MAT1 17 PIO1_2/CT32B1_MAT2 34 PIO1_3/CT32B1_MAT3 50 PIO1_4/CT32B1_CAP0 16 PIO1_5/CT32B1_CAP1 32 PIO1_7 6 PIO1_8 39 PIO1_10 12 PIO1_11 43 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO0_18 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description (LPC1315/16/ USB) Symbol PIO1_13/DTR/ 47 CT16B0_MAT0/TXD PIO1_14/DSR/ 49 CT16B0_MAT1/RXD PIO1_15/DCD/ 57 CT16B0_MAT2/SCK1 PIO1_16/RI/CT16B0_CAP0 63 PIO1_17/CT16B0_CAP1/ 23 RXD PIO1_18/CT16B1_CAP1/ 28 TXD PIO1_19/DTR/SSEL1 3 PIO1_20/DSR/SCK1 18 PIO1_21/DCD/MISO1 35 PIO1_22/RI/MOSI1 51 PIO1_23/CT16B1_MAT1/ 24 SSEL1 PIO1_24/CT32B0_MAT0 27 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO1_13 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description (LPC1315/16/ USB) Symbol PIO1_25/CT32B0_MAT1 2 PIO1_26/CT32B0_MAT2/ 14 RXD PIO1_27/CT32B0_MAT3/ 15 TXD PIO1_28/CT32B0_CAP0/ 31 SCLK PIO1_29/SCK0/ 41 CT32B0_CAP1 PIO1_31 - n.c. 25 n.c. 26 XTALIN 8 XTALOUT DDA VREFN 48 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO1_25 — General purpose digital input/output pin CT32B0_MAT1 — Match output 1 for 32-bit timer 0. ...
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... NXP Semiconductors Table 3. Pin description (LPC1315/16/ USB) Symbol VREFP SSA V 10 [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. ...
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... NXP Semiconductors Table 4. Pin description (LPC1345/46/47 - with USB) Symbol RESET/PIO0_0 4 PIO0_1/CLKOUT/ 5 CT32B0_MAT2/ USB_FTOGGLE PIO0_2/SSEL0/ 13 CT16B0_CAP0 PIO0_3/USB_VBUS 19 PIO0_4/SCL 20 PIO0_5/SDA 21 PIO0_6/USB_CONNECT/ 29 SCK0 PIO0_7/CTS 30 PIO0_8/MISO0/ 36 CT16B0_MAT0 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ RESET — External reset input with 20 ns glitch filter. A ...
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... NXP Semiconductors Table 4. Pin description (LPC1345/46/47 - with USB) Symbol PIO0_9/MOSI0/ 37 CT16B0_MAT1/ SWO SWCLK/PIO0_10/SCK0/ 38 CT16B0_MAT2 TDI/PIO0_11/AD0/ 42 CT32B0_MAT3 TMS/PIO0_12/AD1/ 44 CT32B1_CAP0 TDO/PIO0_13/AD2/ 45 CT32B1_MAT0 TRST/PIO0_14/AD3/ 46 CT32B1_MAT1 SWDIO/PIO0_15/AD4/ 52 CT32B1_MAT2 PIO0_16/AD5/ 53 CT32B1_MAT3/WAKEUP LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO0_9 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 4. Pin description (LPC1345/46/47 - with USB) Symbol PIO0_17/RTS/ 60 CT32B0_CAP0/SCLK PIO0_18/RXD/ 61 CT32B0_MAT0 PIO0_19/TXD/ 62 CT32B0_MAT1 PIO0_20/CT16B1_CAP0 11 PIO0_21/CT16B1_MAT0/ 22 MOSI1 PIO0_22/AD6/ 40 CT16B1_MAT1/MISO1 PIO0_23/AD7 56 PIO1_0/CT32B1_MAT0 1 PIO1_1/CT32B1_MAT1 17 PIO1_2/CT32B1_MAT2 34 PIO1_3/CT32B1_MAT3 50 PIO1_4/CT32B1_CAP0 16 PIO1_5/CT32B1_CAP1 32 PIO1_7 6 PIO1_8 39 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO0_17 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 4. Pin description (LPC1345/46/47 - with USB) Symbol PIO1_10 12 PIO1_11 43 PIO1_13/DTR/ 47 CT16B0_MAT0/TXD PIO1_14/DSR/ 49 CT16B0_MAT1/RXD PIO1_15/DCD/ 57 CT16B0_MAT2/SCK1 PIO1_16/RI/CT16B0_CAP0 63 PIO1_17/CT16B0_CAP1/ 23 RXD PIO1_18/CT16B1_CAP1/ 28 TXD PIO1_19/DTR/SSEL1 3 PIO1_20/DSR/SCK1 18 PIO1_21/DCD/MISO1 35 PIO1_22/RI/MOSI1 51 PIO1_23/CT16B1_MAT1/ 24 SSEL1 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO1_10 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 4. Pin description (LPC1345/46/47 - with USB) Symbol PIO1_24/CT32B0_MAT0 27 PIO1_25/CT32B0_MAT1 2 PIO1_26/CT32B0_MAT2/ 14 RXD PIO1_27/CT32B0_MAT3/ 15 TXD PIO1_28/CT32B0_CAP0/ 31 SCLK PIO1_29/SCK0/ 41 CT32B0_CAP1 PIO1_31 - USB_DM 25 USB_DP 26 XTALIN 8 XTALOUT DDA VREFN 48 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Description [ I/O PIO1_24 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 4. Pin description (LPC1345/46/47 - with USB) Symbol VREFP SSA V 10 [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. ...
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... NXP Semiconductors 7. Functional description 7.1 On-chip flash programming memory The LPC1315/16/17/45/46/47 contain on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. Flash updates via USB are supported as well. ...
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... NXP Semiconductors LPC1315/16/17/45/46/ reserved private peripheral bus reserved GPIO reserved USB APB peripherals 1 GB reserved 2 kB USB SRAM (LPC134x) reserved 2 kB SRAM1 (LPC1317/47) 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM0 reserved 64 kB on-chip flash (LPC1317/47 on-chip flash (LPC1316/46 on-chip flash (LPC1315/45 Fig 8 ...
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... NXP Semiconductors • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function ...
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... NXP Semiconductors 7.8.1 Features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • ...
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... NXP Semiconductors The USART includes full modem control, support for synchronous mode, and a smart card interface. The RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz ...
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... NXP Semiconductors receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it. 7.12.1 Features • The I interface supports Fast-mode Plus with bit rates Mbit/s. ...
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... NXP Semiconductors 7.14.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four match registers per timer that allow: – ...
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... NXP Semiconductors 7.17.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ...
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... NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) system oscillator USBPLLCLKSEL (USB clock select) The USB clock divider is available on parts LPC1345/46/47 only. Fig 9. LPC1315/16/17/45/46/47 clocking generation block diagram 7.18.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU ...
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... NXP Semiconductors Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC1315/16/17/45/46/47 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... NXP Semiconductors controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application ...
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... NXP Semiconductors 7.18.5.4 Power-down mode In Power-down mode, the LPC1315/16/17/45/46/ Sleep-mode and all peripheral clocks and all clock sources are off with the exception of watchdog oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the user has the option to keep the BOD circuit running for BOD protection ...
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... NXP Semiconductors 7.18.6.3 Code security (Code Read Protection - CRP) This feature of the LPC1315/16/17/45/46/47 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP ...
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... NXP Semiconductors The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC1315/16/17/45/46/ reset. Remark: Boundary scan operations should not be started until 250 s after POR, and the test TAP should be reset after the boundary scan ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) ...
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... NXP Semiconductors Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I pull-up current C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output OL current I LOW-level output OL current ...
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... NXP Semiconductors [3] System oscillator enabled; PLL and IRC disabled. [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [6] BOD disabled. [7] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block. ...
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... NXP Semiconductors 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC1315/16/17/45/46/47 user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIOnDIR registers. ...
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... NXP Semiconductors I DD (mA) Fig 11. Typical supply current versus temperature in Active mode I DD (mA) Fig 12. Typical supply current versus temperature in Sleep mode LPC1315_16_17_45_46_47 Product data sheet 18 14.4 10.8 7.2 3.6 0 -40 -15 10 Conditions 3.3 V; Active mode entered executing code DD pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register ...
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... NXP Semiconductors I DD (μA) Fig 13. Typical supply current versus temperature in Deep-sleep mode I DD (μA) Fig 14. Typical supply current versus temperature in Power-down mode LPC1315_16_17_45_46_47 Product data sheet 300 290 280 270 260 250 -40 -15 10 Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register ...
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... NXP Semiconductors I DD (μA) Fig 15. Typical supply current versus temperature in Deep power-down mode Table 8. Power consumption for individual analog and digital blocks The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed ...
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... NXP Semiconductors Table 8. Power consumption for individual analog and digital blocks The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed ...
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... NXP Semiconductors (mA) Fig 17. I (mA) Fig 18. Typical LOW-level output current I LPC1315_16_17_45_46_47 Product data sheet 0.2 Conditions 3 pins PIO0_4 and PIO0_5 C-bus pins (high current sink): Typical LOW-level output current I LOW-level output voltage 0.2 Conditions 3.3 V; standard port pins and PIO0_7. ...
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... NXP Semiconductors V Fig 19. Typical HIGH-level output voltage V (μA) Fig 20. Typical pull-up current I LPC1315_16_17_45_46_47 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V ...
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... NXP Semiconductors (μA) Fig 21. Typical pull-down current I LPC1315_16_17_45_46_47 Product data sheet ° °C −40 ° Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 September 2012 LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash/EEPROM memory Table 9. amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 10. amb Symbol ...
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... NXP Semiconductors Fig 22. External clock timing (with an amplitude of at least V LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/ CHCL CLCX All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 September 2012 32-bit ARM Cortex-M3 microcontroller t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV) i(RMS) © NXP B.V. 2012. All rights reserved. ...
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... NXP Semiconductors 10.3 Internal oscillators Table 12. amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. (MHz) Fig 23. Internal RC oscillator frequency versus temperature Table 13 ...
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... NXP Semiconductors 10.4 I/O pins Table 14. amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 15. Dynamic characteristic: I [ +85 C. amb Symbol Parameter f SCL clock SCL frequency t fall time f LOW period of the t LOW SCL clock ...
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... NXP Semiconductors could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t [8] The maximum t HD;DAT transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. ...
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... NXP Semiconductors 10.6 SSP interface Table 16. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter SSP master T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time h(Q) SSP slave T PCLK cycle time cy(PCLK) ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 25. SSP master timing in SPI mode LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 September 2012 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 26. SSP slave timing in SPI mode LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 September 2012 ...
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... NXP Semiconductors 11. ADC electrical characteristics Table 17. ADC characteristics 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia I ADC analog supply current on pin V DDA(ADC) E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 12. Application information 12.1 Suggested USB interface solutions LPC1345/46/47 Fig 28. USB interface on a self-powered device LPC1345/46/47 Fig 29. USB interface on a bus-powered device 12.2 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... NXP Semiconductors Fig 30. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...
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... NXP Semiconductors Table 18. Fundamental oscillation frequency F 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 19. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 12.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane ...
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... NXP Semiconductors 12.4 Standard I/O pad configuration Figure 32 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output driver pin configured as digital input data input pin configured as analog input Fig 32 ...
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... NXP Semiconductors 12.5 Reset pad configuration Fig 33. Reset pad configuration 12.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1315/16/17/45/46/47 chip. • ...
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... NXP Semiconductors 13. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 37. Reflow soldering of the HVQFN33 package LPC1315_16_17_45_46_47 Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7.95 CU ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 38. Reflow soldering of the LQFP48 package LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/ (8× Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP64 package solder land occupied area DIMENSIONS 0.500 0.560 13.300 13.300 10.300 10.300 Fig 39. Reflow soldering of the LQFP64 package LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/ (0.125 (8× ...
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... NXP Semiconductors 15. Abbreviations Table 20. Acronym A/D ADC AHB APB BOD CDC ETM GPIO HID JTAG MSC PLL RC SPI SSI SSP TAP USART LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection ...
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... NXP Semiconductors 16. Revision history Table 21. Revision history Document ID LPC1315_16_17_45_46_47 v.3 LPC1315_16_17_45_46_47 v.2 Modifications: LPC1315_16_17_45_46_47 v.1 LPC1315_16_17_45_46_47 Product data sheet LPC1315/16/17/45/46/47 Release date Data sheet status 20120920 Product data sheet • Reflow soldering drawing corrected for the HVQFN33 package. See • BOD interrupt trigger level 0 removed. See • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Functional description . . . . . . . . . . . . . . . . . . 24 7.1 On-chip flash programming memory . . . . . . . 24 7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 Memory map 7.6 Nested Vectored Interrupt Controller (NVIC) ...
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... NXP Semiconductors 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...