LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet
LPC1112FHN33/203,5
Specifications of LPC1112FHN33/203,5
Related parts for LPC1112FHN33/203,5
LPC1112FHN33/203,5 Summary of contents
Page 1
UM10398 LPC111x/LPC11Cxx User manual Rev. 12 — 24 September 2012 Document information Info Content Keywords ARM Cortex-M0, LPC1111, LPC1112, LPC1113, LPC1114, LPC11C12, LPC11C14, LPC1100, LPC1100L, LPC11C00, LPC11C22, LPC11C24, LPC11D14, LPC1100XL Abstract LPC111x/LPC11Cxx User manual User manual ...
Page 2
... NXP Semiconductors Revision history Rev Date Description 12 20120924 LPC111x/LPC11C1x/LPC11C2x User manual • Modifications: BOD level 0 for reset added. See • Description of the TEMT bit in the UART LSR register updated. See 11 20120726 LPC111x/LPC11C1x/LPC11C2x User manual • Modifications: Function SSEL1 added to pin PIO2_0 in Table 170 and Figure 28. ...
Page 3
UM10398 Chapter 1: LPC111x/LPC11Cxx Introductory information Rev. 12 — 24 September 2012 1.1 Introduction The LPC111x/LPC11Cxx are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing ...
Page 4
... NXP Semiconductors Table 1. Series LPC1100 series LPC1100L series LPC1100XL series LPC11C00 series LPC1100 series features plus the following additional features: LPC11D14 (LPC1100L series) UM10398 User manual Chapter 1: LPC111x/LPC11Cxx Introductory information LPC111x/LPC11Cxx feature changes Features overview • I2C, SSP, UART, GPIO • ...
Page 5
... NXP Semiconductors 1.2 Features • System: – ARM Cortex-M0 processor, running at frequencies MHz. – ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). – Serial Wire Debug. – System tick timer. • Memory: – On-chip flash programming memory for LPC1100, LPC1100L, and LPC1100C series (LPC1114/LPC11C14 (LPC1113 (LPC1112/LPC11C12 (LPC1111), 4kB (LPC1110) ...
Page 6
... NXP Semiconductors – Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. – PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. – Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. • ...
Page 7
... NXP Semiconductors 1.3 Ordering information Table 2. Ordering information Type number Package Name SO20, TSSOP20, TSSOP28, and DIP28 packages LPC1110FD20 SO20 LPC1111FDH20/002 TSSOP20 LPC1112FD20/102 SO20 LPC1112FDH20/102 TSSOP20 LPC1112FDH28/102 TSSOP28 LPC1114FDH28/102 TSSOP28 LPC1114FN28/102 DIP28 HVQFN24/33 and LQFP48 packages LPC1111FHN33/101 HVQFN33 LPC1111FHN33/102 HVQFN33 LPC1111FHN33/201 HVQFN33 ...
Page 8
... NXP Semiconductors Table 2. Ordering information …continued Type number Package Name LPC1113FHN33/201 HVQFN33 LPC1113FHN33/202 HVQFN33 LPC1113FHN33/301 HVQFN33 LPC1113FHN33/302 HVQFN33 LPC1113FHN33/203 HVQFN33 LPC1113FHN33/303 HVQFN33 LPC1114FHN33/201 HVQFN33 LPC1114FHN33/202 HVQFN33 LPC1114FHN33/301 HVQFN33 LPC1114FHN33/302 HVQFN33 LPC1114FHI33/302 HVQFN33 LPC1114FHI33/303 HVQFN33 LPC1114FHN33/203 HVQFN33 LPC1114FHN33/303 HVQFN33 LPC1114FHN33/333 HVQFN33 LPC1113FBD48/301 ...
Page 9
... NXP Semiconductors Table 2. Ordering information …continued Type number Package Name LPC1114FBD48/323 LQFP48 LPC1114FBD48/333 LQFP48 LPC1115FBD48/303 LQFP48 Table 3. Ordering options Type number Series LPC1110 LPC1110FD20 LPC1100L LPC1111 LPC1111FDH20/002 LPC1100L LPC1111FHN33/101 LPC1100 LPC1111FHN33/102 LPC1100L LPC1111FHN33/103 LPC1100XL 8 kB LPC1111FHN33/201 LPC1100 LPC1111FHN33/202 LPC1100L LPC1111FHN33/203 LPC1100XL 8 kB ...
Page 10
... NXP Semiconductors Table 3. Ordering options …continued Type number Series LPC1113FHN33/302 LPC1100L LPC1113FHN33/303 LPC1100XL 24 kB LPC1113FBD48/301 LPC1100 LPC1113FBD48/302 LPC1100L LPC1113FBD48/303 LPC1100XL 24 kB LPC1114 LPC1114FDH28/102 LPC1100L LPC1114FN28/102 LPC1100L LPC1114FHN33/201 LPC1100 LPC1114FHN33/202 LPC1100L LPC1114FHN33/203 LPC1100XL 32 kB LPC1114FHN33/301 LPC1100 LPC1114FHN33/302 LPC1100L LPC1114FHN33/303 LPC1100XL 32 kB LPC1114FHN33/333 ...
Page 11
... NXP Semiconductors 1.4 Block diagram LPC1110/11/12/13/14 HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (5) DTR, DSR, CTS , (5) DCD, RI, RTS (3) CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 (3) CT32B0_CAP0 (3) CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 (3) CT32B1_CAP0 (3) CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 (3) CT16B0_CAP0 (3) CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 (3) CT16B1_CAP0 (1) LQFP48 packages only. (2) Not on LPC1112FDH20/102. ...
Page 12
... NXP Semiconductors LPC1111/12/13/14/15XL system bus slave HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD UART (1) DTR, DSR , CTS, (1) (1) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP[1:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP[1:0] CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP[1:0] CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP[1:0] (1) Available on LQFP packages only. ...
Page 13
... NXP Semiconductors LPC11Cxx LPC11D14 system bus slave HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD UART DTR, DSR, CTS, DCD, RI, RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 (1) CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 CAN_TXD C_CAN (LPC11C12/C14) CAN_RXD CANL, CANH ...
Page 14
... NXP Semiconductors PIO0, PIO1, PIO2, PIO3 Fig 4. LPC11D14 block diagram V LCD LCD BIAS GENERATOR V SS(LCD) CLK CLOCK SELECT AND TIMING SYNC OSC V SS(LCD) OSCILLATOR V DD(LCD) LCD_SCL INPUT FILTERS LCD_SDA Fig 5. PCF8576D block diagram UM10398 User manual Chapter 1: LPC111x/LPC11Cxx Introductory information LPC1114 ...
Page 15
... NXP Semiconductors 1.5 ARM Cortex-M0 processor The ARM Cortex-M0 processor is described in detail in Cortex-M0 processor and core Cortex-M0 processor core is configured as follows: • System options: – The Nested Vectored Interrupt Controller (NVIC) is included and supports interrupts. – The system tick timer is included. ...
Page 16
UM10398 Chapter 2: LPC111x/LPC11Cxx Memory mapping Rev. 12 — 24 September 2012 2.1 How to read this chapter Table 4 and parts. Table 4. Part Suffix LPC1111 LPC1112 LPC1113 LPC1114/LPC11D14 LPC1114/323 LPC1114/333 LPC1115 Table 5. Part LPC11C12/301 LPC11C14/301 LPC11C22/301 LPC11C24/301 ...
Page 17
... NXP Semiconductors LPC1111/12/13/14 LPC11Cxx LPC11D14 4 GB reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC1113/14/301/302; LPC11D14; LPC11Cxx SRAM (LPC1111/12/13/14/201/202 SRAM (LPC1111/12/101/102) reserved 32 kB on-chip flash (LPC1114; LPC11D14; ...
Page 18
... NXP Semiconductors LPC1111/12/13/14/15XL 4 GB reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC1113/14/15/303/323/333 SRAM (LPC1111/12/13/14/203 SRAM (LPC1111/12/103) reserved 64 kB on-chip flash (LPC1115 on-chip flash (LPC1114/333) ...
Page 19
UM10398 Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON) Rev. 12 — 24 September 2012 3.1 How to read this chapter The following functions of the system configuration block depend on the specific part number: DEVICE_ID register The DEVICE_ID register is valid ...
Page 20
... NXP Semiconductors Table 6. Pin name CLKOUT PIO0_0 to PIO0_11 PIO1_0 3.4 Clock generation See Figure 8 The LPC111x/LPC11Cxx include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. ...
Page 21
... NXP Semiconductors IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL sys_pllclkin system oscillator SYSPLLCLKSEL (system PLL clock select) Fig 8. LPC111x/LPC11Cxx CGU block diagram 3.5 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. ...
Page 22
... NXP Semiconductors Table 7. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description SYSOSCCTRL R/W 0x020 WDTOSCCTRL R/W 0x024 IRCCTRL R/W 0x028 - - 0x02C SYSRSTSTAT R/W 0x030 - - 0x034 - 0x03C SYSPLLCLKSEL R/W 0x040 SYSPLLCLKUEN R/W 0x044 - - 0x048 - 0x06C MAINCLKSEL R/W 0x070 MAINCLKUEN R/W 0x074 SYSAHBCLKDIV R/W 0x078 - - 0x07C ...
Page 23
... NXP Semiconductors Table 7. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description - - 0x210 - 0x22C PDSLEEPCFG R/W 0x230 PDAWAKECFG R/W 0x234 PDRUNCFG R/W 0x238 - - 0x23C - 0x3F0 DEVICE_ID R 0x3F4 3.5.1 System memory remap register The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, or the SRAM ...
Page 24
... NXP Semiconductors Table 9. Bit Symbol 1 I2C_RST_N 2 SSP1_RST_N 3 CAN_RST_N 31:4 - 3.5.3 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and memories ...
Page 25
... NXP Semiconductors Table 11. Bit Symbol 0 LOCK 31:1 - 3.5.5 System oscillator control register This register configures the frequency range for the system oscillator. Table 12. Bit Symbol 0 BYPASS 1 FREQRANGE 31:2 - 3.5.6 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part ...
Page 26
... NXP Semiconductors Table 13. Bit Symbol 4:0 DIVSEL 8:5 FREQSEL 31:9 - 3.5.7 Internal resonant crystal control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. Table 14. Bit Symbol 7:0 TRIM 31:8 - 3.5.8 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. Write a one to clear the reset ...
Page 27
... NXP Semiconductors The reset value given in Table 15. Bit Symbol 0 POR 1 EXTRST 2 WDT 3 BOD 4 SYSRST 31:5 - 3.5.9 System PLL clock source select register This register selects the clock source for the system PLL. The SYSPLLCLKUEN register (see Section Remark: When switching clock sources, both clocks must be running before the clock source is updated ...
Page 28
... NXP Semiconductors 3.5.10 System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN. ...
Page 29
... NXP Semiconductors Table 19. Bit Symbol 0 ENA 31:1 - 3.5.13 System AHB clock divider register This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0. Table 20. ...
Page 30
... NXP Semiconductors Table 21. Bit Symbol 4 FLASHARRAY 5 I2C 6 GPIO 7 CT16B0 8 CT16B1 9 CT32B0 10 CT32B1 11 SSP0 12 UART 13 ADC WDT 16 IOCON UM10398 User manual Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON) System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Value Description Enables clock for flash array access. ...
Page 31
... NXP Semiconductors Table 21. Bit Symbol 17 CAN 18 SSP1 31:19 - 3.5.15 SPI0 clock divider register This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be shut down by setting the DIV bits to 0x0. Table 22. Bit Symbol 7:0 DIV 31:8 - 3.5.16 UART clock divider register This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can be shut down by setting the DIV bits to 0x0 ...
Page 32
... NXP Semiconductors Table 24. Bit Symbol 7:0 DIV 31:8 - 3.5.18 WDT clock source select register This register selects the clock source for the watchdog timer. The WDTCLKUEN register (see Section Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 25. ...
Page 33
... NXP Semiconductors Table 27. Bit Symbol 7:0 DIV 31:8 - 3.5.21 CLKOUT clock source select register This register configures the clkout_clk signal to be output on the CLKOUT pin. All three oscillators and the main clock can be selected for the clkout_clk clock. The CLKOUTCLKUEN register (see for the update to take effect. ...
Page 34
... NXP Semiconductors 3.5.23 CLKOUT clock divider register This register determines the divider value for the clock output signal on the CLKOUT pin. Table 30. Bit Symbol 7:0 DIV 31:8 - 3.5.24 POR captured PIO status register 0 The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset ...
Page 35
... NXP Semiconductors 3.5.26 BOD control register The BOD control register selects up to four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed are typical values. Table 33. Bit Symbol 1:0 BODRSTLEV 3:2 BODINTVAL 4 BODRSTENA 31:5 - 3.5.27 System tick counter calibration register This register determines the value of the SYST_CALIB register (see Table 34 ...
Page 36
... NXP Semiconductors Table 35. Bit Symbol Description 4:0 IRQNO 30 NMIEN Note: If the NMISRC register is used to select an interrupt as the source of Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a Non-Maskable and a normal interrupt. Avoid this situation by disabling the normal interrupt in the NVIC, as described in 3 ...
Page 37
... NXP Semiconductors Table 37. Bit Symbol 11:0 ERPIO0_n 12 ERPIO1_0 31:13 - 3.5.31 Start logic reset register 0 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt for waking up from Deep-sleep mode ...
Page 38
... NXP Semiconductors 3.5.33 Deep-sleep mode configuration register This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode. This register must be initialized at least once before entering Deep-sleep mode with one of the four values shown in Table 40. ...
Page 39
... NXP Semiconductors Table 41. Bit Symbol 10:8 NOTUSED 12:11 NOTUSED 31:13 - 3.5.34 Wake-up configuration register The bits in this register determine the state the chip enters when it is waking up from Deep-sleep mode. By default, the IRC and flash memory are powered and running and the BOD circuit is enabled when the chip wakes up from Deep-sleep mode. ...
Page 40
... NXP Semiconductors Table 42. Bit Symbol 15:13 - 31:16 - 3.5.35 Power-down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC. ...
Page 41
... NXP Semiconductors Table 43. Bit Symbol 6 WDTOSC_PD 7 SYSPLL_PD 15:13 - 31:16 - 3.5.36 Device ID register This device ID register is a read-only register and contains the part ID for each LPC111x/LPC11Cxx part. This register is also read by the ISP/IAP commands (Section 26.5.11). Remark: This register returns the part ID for parts of the LPC1100, LPC1100C, and LPC1100L series only ...
Page 42
... NXP Semiconductors – 0x0425 502B = LPC1112FHN33/201 – 0x2524 902B = LPC1112FHN33/201; LPC1112FHN33/202; LPC1112FHI33/202; LPC1112FHN24/202 • LPC1113 – 0x0434 502B = LPC1113FHN33/201 – 0x2532 902B = LPC1113FHN33/201; LPC1113FHN33/202 – 0x0434 102B = LPC1113FHN33/301; LPC1113FBD48/301 – 0x2532 102B = LPC1113FHN33/301; LPC1113FHN33/302; LPC1113FBD48/301; LPC1113FBD48/302 • LPC1114 – 0x0A40 902B = LPC1114FDH28/102; LPC1114FN28/102 – ...
Page 43
... NXP Semiconductors 3. The boot code in the ROM starts. The boot code performs the boot tasks and may jump to the flash. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values ...
Page 44
... NXP Semiconductors 3.9 Power management The LPC111x/LPC11Cxx support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. ...
Page 45
... NXP Semiconductors • The system clock frequency remains the same as in Active mode, but the processor is not clocked. • Analog and digital peripherals are selected as in Active mode. 3.9.2.2 Programming Sleep mode The following steps must be performed to enter Sleep mode: 1. The DPDEN bit in the PCON register must be set to zero 2 ...
Page 46
... NXP Semiconductors 2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG register timer-controlled wake-up is needed, ensure that the watchdog oscillator is powered in the PDRUNCFG register and switch the clock source to WD oscillator in the MAINCLKSEL register timer-controlled wake-up is needed and the watchdog oscillator is shut down, ...
Page 47
... NXP Semiconductors All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin. 3.9.4.1 Power configuration in Deep power-down mode Deep power-down mode has no configuration options. All clocks, the core, and all peripherals are powered down. Only the WAKEUP pin is powered. ...
Page 48
... NXP Semiconductors 3.10 Deep-sleep mode details 3.10.1 IRC oscillator The IRC is the only oscillator on the LPC111x/LPC11Cxx that can always shut down glitch-free. Therefore it is recommended that the user switches the clock source to IRC before the chip enters Deep-sleep mode. 3.10.2 Start logic The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM core ...
Page 49
... NXP Semiconductors 8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register 9. Start the counter/timer. 10. Use the ARM WFI instruction to enter Deep-sleep mode. 3.11 System PLL functional description The LPC111x/LPC11Cxx uses the system PLL to create the clocks for the core and peripherals. ...
Page 50
... NXP Semiconductors row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal. ...
Page 51
... NXP Semiconductors 3.11.4.1 Normal mode In normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations: To select the appropriate values for M and recommended to follow these steps: 1. Specify the input clock frequency FCLKIN. 2. Calculate M to obtain the desired output frequency FCLKOUT with M = FCLKOUT / FCLKIN. 3. Find a value so that FCCO = 2 ...
Page 52
... NXP Semiconductors Table 47. Bit Symbol 1:0 FLASHTIM 31:2 - UM10398 User manual Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON) Flash configuration register (FLASHCFG, address 0x4003 C010) bit description Valu Description e Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access system clock flash access time (for system clock frequencies MHz) ...
Page 53
UM10398 Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU) Rev. 12 — 24 September 2012 4.1 How to read this chapter Remark: For parts LPC11(D)1x/102/202/302, also refer to 4.2 Introduction The PMU controls the Deep power-down mode. Four general purpose register ...
Page 54
... NXP Semiconductors Table 49. Bit Symbol 8 SLEEPFLAG 10 DPDFLAG 31:12 - 4.3.2 General purpose registers The general purpose registers retain data through the Deep power-down mode when power is still applied to the V Only a “cold” boot when all power has been completely removed from the chip will reset the general purpose registers ...
Page 55
... NXP Semiconductors Table 51. Bit Symbol 10 WAKEUPHYS 31:11 GPDATA 4.4 Functional description For details of entering and exiting Deep power-down mode, see UM10398 User manual Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU) General purpose register 4 (GPREG4, address 0x4003 8014) bit description Value Description WAKEUP pin hysteresis enable 1 Hysteresis for WAKEUP pin enabled ...
Page 56
UM10398 Chapter 5: LPC111x/LPC11Cxx Power profiles Rev. 12 — 24 September 2012 5.1 How to read this chapter The power profiles are available for parts LPC11(D)1x/102/202/302 only (LPC1100L series). 5.2 Features • Includes ROM-based application services • Power Management services ...
Page 57
... NXP Semiconductors irc_osc_clk wdt_osc_clk MAINCLKSEL sys_pllclkout irc_osc_clk SYS PLL sys_osc_clk sys_pllclkin SYSPLLCLKSEL Fig 12. LPC111x/102/202/302 clock configuration for power API use 5.4 Definitions The following elements have to be defined in an application that uses the power profiles: typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]); ...
Page 58
... NXP Semiconductors The routine returns a result code that indicates if the system PLL was successfully set (PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong). The current system frequency value is also returned. The application should use this information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or clockout) ...
Page 59
... NXP Semiconductors CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities. CPU_FREQ_APPROX results in a system clock that is as close as possible to the requested value (it may be greater than or less than the requested value). ...
Page 60
... NXP Semiconductors command[ (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300, set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings ...
Page 61
... NXP Semiconductors The above code specifies a 12 MHz PLL input clock, a system clock of approximately 16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 16000 in result[1]. The new system clock is 16 MHz. 5.6 Power routine 5.6.1 set_power This routine configures the device’s internal power control settings according to the calling arguments ...
Page 62
... NXP Semiconductors Table 53. Routine Input Result The following definitions are needed for set_power routine calls: /* set_power mode options */ #define #define #define #define /* set_power result0 options */ #define #define #define For a simplified clock configuration scheme see 5.6.1.1 Param0: main clock The main clock is the clock rate the microcontroller uses to source the system’s and the peripherals’ ...
Page 63
... NXP Semiconductors 5.6.1.4 Code examples The following examples illustrate some of the set_power features discussed above. 5.6.1.4.1 Invalid frequency (device maximum clock rate exceeded) command[0] = 60; command[1] = PWR_CPU_PERFORMANCE; command[2] = 60; (*rom)->pWRD->set_power(command, result); The above setup would be used in a system running at the main and system clock of 60 MHz, with a need for maximum CPU processing power ...
Page 64
UM10398 Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt Controller (NVIC) Rev. 12 — 24 September 2012 6.1 How to read this chapter The C_CAN controller interrupt is available on parts LPC11Cxx only. 6.2 Introduction The Nested Vectored Interrupt Controller (NVIC) is ...
Page 65
... NXP Semiconductors Table 54. Exception Number UM10398 User manual Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt Controller Connection of interrupt sources to the Vectored Interrupt Controller Vector Function Flag(s) Offset CT16B0 Match Capture 0 CT16B1 Match Capture 0 ...
Page 66
UM10398 Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration (IOCONFIG) Rev. 12 — 24 September 2012 7.1 How to read this chapter Remark: This chapter applies to parts in the following series (see • LPC1100 • LPC1100L • LPC1100C • LPC11D14 Pin ...
Page 67
... NXP Semiconductors • Pseudo open-drain mode for non-I2C pins (see 7.3 General description The IOCON registers control the function (GPIO or peripheral function), the input mode, and the hysteresis of all PIOn_m pins. In addition, the I 2 different I C-bus modes pin is used as input pin for the ADC, an analog input mode can be selected ...
Page 68
... NXP Semiconductors 7.3.2 Pin mode The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode. The possible on-chip resistor configurations are pull-up enabled, pull-down enabled pull-up/pull-down. The default value is pull-up enabled. See details ...
Page 69
... NXP Semiconductors 7.3.6 Open-drain Mode When output is selected, either by selecting a special function in the FUNC field selecting GPIO function for a pin having its GPIODIR register the OD bit selects open-drain operation, that is disables the high-drive transistor. This option has no effect on the primary I Remark: The open-drain mode is not available on all parts (see 7 ...
Page 70
... NXP Semiconductors Table 55. Register overview: I/O configuration (base address 0x4004 4000) Name Access IOCON_PIO0_5 R/W IOCON_PIO1_9 R/W IOCON_PIO3_4 R/W IOCON_PIO2_4 R/W IOCON_PIO2_5 R/W IOCON_PIO3_5 R/W IOCON_PIO0_6 R/W IOCON_PIO0_7 R/W IOCON_PIO2_9 R/W IOCON_PIO2_10 R/W IOCON_PIO2_2 R/W IOCON_PIO0_8 R/W IOCON_PIO0_9 R/W IOCON_SWCLK_PIO0_10 R/W IOCON_PIO1_10 R/W IOCON_PIO2_11 R/W IOCON_R_PIO0_11 R/W IOCON_R_PIO1_0 R/W IOCON_R_PIO1_1 R/W IOCON_R_PIO1_2 R/W IOCON_PIO3_0 R/W IOCON_PIO3_1 R/W IOCON_PIO2_3 R/W IOCON_SWDIO_PIO1_3 R/W IOCON_PIO1_4 R/W IOCON_PIO1_11 R/W IOCON_PIO3_2 R/W IOCON_PIO1_5 R/W UM10398 ...
Page 71
... NXP Semiconductors Table 55. Register overview: I/O configuration (base address 0x4004 4000) Name Access IOCON_PIO1_6 R/W IOCON_PIO1_7 R/W IOCON_PIO3_3 R/W IOCON_SCK_LOC R/W IOCON_DSR_LOC R/W IOCON_DCD_LOC R/W IOCON_RI_LOC R/W Table 56. I/O configuration registers ordered by port number Port pin Register name PIO0_0 IOCON_RESET_PIO0_0 PIO0_1 IOCON_PIO0_1 PIO0_2 IOCON_PIO0_2 PIO0_3 IOCON_PIO0_3 PIO0_4 IOCON_PIO0_4 PIO0_5 IOCON_PIO0_5 ...
Page 72
... NXP Semiconductors Table 56. I/O configuration registers ordered by port number Port pin Register name PIO2_2 IOCON_PIO2_2 PIO2_3 IOCON_PIO2_3 PIO2_4 IOCON_PIO2_4 PIO2_5 IOCON_PIO2_5 PIO2_6 IOCON_PIO2_6 PIO2_7 IOCON_PIO2_7 PIO2_8 IOCON_PIO2_8 PIO2_9 IOCON_PIO2_9 PIO2_10 IOCON_PIO2_10 PIO2_11 IOCON_PIO2_11 PIO3_0 IOCON_PIO3_0 PIO3_1 IOCON_PIO3_1 PIO3_2 IOCON_PIO3_2 PIO3_3 IOCON_PIO3_3 PIO3_4 ...
Page 73
... NXP Semiconductors Table 57. Bit Symbol 10 OD 31:11 - 7.4.2 IOCON_PIO2_0 Table 58. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.3 IOCON_PIO_RESET_PIO0_0 Table 59. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description Value Description Selects pseudo open-drain mode. See specific details ...
Page 74
... NXP Semiconductors Table 59. Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 7.4.4 IOCON_PIO0_1 Table 60. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) bit description Value Description Selects function mode (on-chip pull-up/pull-down resistor control). ...
Page 75
... NXP Semiconductors 7.4.5 IOCON_PIO1_8 Table 61. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.6 IOCON_PIO0_2 Table 62. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description Value Description Selects pin function. All other values are reserved. ...
Page 76
... NXP Semiconductors Table 62. Bit Symbol 10 OD 31:11 - 7.4.7 IOCON_PIO2_7 Table 63. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.8 IOCON_PIO2_8 Table 64. Bit Symbol 2:0 FUNC 4:3 MODE UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description Value Description Selects pseudo open-drain mode. See specific details ...
Page 77
... NXP Semiconductors Table 64. Bit Symbol 5 HYS 9 31:11 - 7.4.9 IOCON_PIO2_1 Table 65. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description Value Description Hysteresis. 0 Disable. 1 Enable. - Reserved Selects pseudo open-drain mode. See specific details ...
Page 78
... NXP Semiconductors 7.4.10 IOCON_PIO0_3 Table 66. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.11 IOCON_PIO0_4 Table 67. Bit Symbol 2:0 FUNC 7:3 9:8 I2CMODE 31:10 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description Value Description Selects pin function. All other values are reserved. ...
Page 79
... NXP Semiconductors 7.4.12 IOCON_PIO0_5 Table 68. Bit Symbol 2:0 FUNC 7:3 9:8 I2CMODE 31:10 - 7.4.13 IOCON_PIO1_9 Remark: See Table 69. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.14 IOCON_PIO3_4 Remark: See UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description Value Description Selects pin function. All other values are reserved. ...
Page 80
... NXP Semiconductors Table 70. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.15 IOCON_PIO2_4 Remark: See Table 71. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description Value Description Selects pin function. All other values are reserved. ...
Page 81
... NXP Semiconductors 7.4.16 IOCON_PIO2_5 Remark: See Table 72. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.17 IOCON_PIO3_5 Remark: See Table 73. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration Section 7.1 for part specific details. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description ...
Page 82
... NXP Semiconductors Table 73. Bit Symbol 10 OD 31:11 - 7.4.18 IOCON_PIO0_6 Table 74. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.19 IOCON_PIO0_7 Table 75. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description Value Description Selects pseudo open-drain mode. See specific details ...
Page 83
... NXP Semiconductors Table 75. Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 7.4.20 IOCON_PIO2_9 Remark: See Table 76. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description Value Description Selects function mode (on-chip pull-up/pull-down resistor control) ...
Page 84
... NXP Semiconductors 7.4.21 IOCON_PIO2_10 Table 77. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.22 IOCON_PIO2_2 Table 78. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit description Value Description Selects pin function. All other values are reserved. ...
Page 85
... NXP Semiconductors Table 78. Bit Symbol 10 OD 31:11 - 7.4.23 IOCON_PIO0_8 Table 79. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.24 IOCON_PIO0_9 Table 80. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description Value Description Selects pseudo open-drain mode. 0 Standard GPIO output ...
Page 86
... NXP Semiconductors Table 80. Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 7.4.25 IOCON_SWCLK_PIO0_10 Table 81. Bit Symbol Value 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description Value Description Selects function mode (on-chip pull-up/pull-down resistor control) ...
Page 87
... NXP Semiconductors 7.4.26 IOCON_PIO1_10 Table 82. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - 7.4.27 IOCON_PIO2_11 Table 83. Bit Symbol 2:0 FUNC 4:3 MODE UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit description Value Description Selects pin function. All other values are reserved. ...
Page 88
... NXP Semiconductors Table 83. Bit Symbol 5 HYS 9 31:11 - 7.4.28 IOCON_R_PIO0_11 Table 84. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description Value Description Hysteresis. 0 Disable. 1 Enable. - Reserved Selects pseudo open-drain mode. See specific details ...
Page 89
... NXP Semiconductors 7.4.29 IOCON_R_PIO1_0 Table 85. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - 7.4.30 IOCON_R_PIO1_1 Table 86. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit description Value Description Selects pin function. All other values are reserved. ...
Page 90
... NXP Semiconductors Table 86. Bit Symbol 4:3 MODE 5 HYS ADMODE 9 31:11 - 7.4.31 IOCON_R_PIO1_2 Table 87. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit description …continued Value Description Selects function mode (on-chip pull-up/pull-down resistor control) ...
Page 91
... NXP Semiconductors Table 87. Bit Symbol 7 ADMODE 9 31:11 - 7.4.32 IOCON_PIO3_0 Table 88. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.33 IOCON_PIO3_1 Table 89. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit description …continued Value Description Selects Analog/Digital mode ...
Page 92
... NXP Semiconductors Table 89. Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 7.4.34 IOCON_PIO2_3 Table 90. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description Value Description Selects function mode (on-chip pull-up/pull-down resistor control). ...
Page 93
... NXP Semiconductors 7.4.35 IOCON_SWDIO_PIO1_3 Table 91. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - 7.4.36 IOCON_PIO1_4 Table 92. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) bit description Value Description Selects pin function. All other values are reserved. ...
Page 94
... NXP Semiconductors Table 92. Bit Symbol 4:3 MODE 5 HYS ADMODE 9 31:11 - 7.4.37 IOCON_PIO1_11 Table 93. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9:8 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description Value Description Selects function mode (on-chip pull-up/pull-down resistor control) ...
Page 95
... NXP Semiconductors Table 93. Bit Symbol 10 OD 31:11 - 7.4.38 IOCON_PIO3_2 Table 94. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.39 IOCON_PIO1_5 Table 95. Bit Symbol 2:0 FUNC UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description Value Description Selects pseudo open-drain mode. See specific details ...
Page 96
... NXP Semiconductors Table 95. Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 7.4.40 IOCON_PIO1_6 Table 96. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description Value Description Selects function mode (on-chip pull-up/pull-down resistor control). ...
Page 97
... NXP Semiconductors 7.4.41 IOCON_PIO1_7 Table 97. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 7.4.42 IOCON_PIO3_3 Table 98. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description Value Description Selects pin function. All other values are reserved. ...
Page 98
... NXP Semiconductors Table 98. Bit Symbol 10 OD 31:11 - 7.4.43 IOCON_SCK_LOC Table 99. Bit Symbol 1:0 SCKLOC 31:2 - 7.4.44 IOCON_DSR_LOC Table 100. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit Bit Symbol 1:0 DSRLOC 31:2 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description ...
Page 99
... NXP Semiconductors 7.4.45 IOCON_DCD_LOC Table 101. IOCON DCD location register (IOCON_DCD_LOC, address 0x4004 40B8) bit Bit Symbol 1:0 DCDLOC 31:2 - 7.4.46 IOCON_RI_LOC Table 102. IOCON RI location register (IOCON_RI_LOC, address 0x4004 40BC) bit Bit Symbol 1:0 RILOC 31:2 - UM10398 User manual Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration description Value Description Selects pin location for DCD function ...
Page 100
UM10398 Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) Rev. 12 — 24 September 2012 8.1 How to read this chapter Remark: This chapter applies to parts in the following series (see • LPC1100XL The implementation of the I/O configuration registers ...
Page 101
... NXP Semiconductors open-drain enable pin configured as digital output driver pin configured as digital input pin configured as analog input Fig 15. Standard I/O pin configuration 8.3.1 Pin function The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000 peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether the pin is configured as an input or output (see function, the pin direction is controlled automatically depending on the pin’ ...
Page 102
... NXP Semiconductors not applicable to the Deep power-down mode. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state temporarily not driven. 8.3.3 Hysteresis The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers (see the LPC1100XL data sheet for details) ...
Page 103
... NXP Semiconductors Some input functions (SCK0, DSR, DCD, RI, SSEL1, CT16B0_CAP0, SCK1, MISO1, MOSI1, CT32B0_CAP0, and RXD) are multiplexed to several physical pins. The IOCON_LOC registers select the pin location for each of these functions. Remark: The IOCON registers are listed in order of their memory locations in which correspond to the order of their physical pin numbers in the LQFP48 package starting at the upper left corner with pin 1 (PIO2_6) ...
Page 104
... NXP Semiconductors Table 103. Register overview: I/O configuration (base address 0x4004 4000) Name Access IOCON_PIO0_7 R/W IOCON_PIO2_9 R/W IOCON_PIO2_10 R/W IOCON_PIO2_2 R/W IOCON_PIO0_8 R/W IOCON_PIO0_9 R/W IOCON_SWCLK_PIO0_10 R/W IOCON_PIO1_10 R/W IOCON_PIO2_11 R/W IOCON_R_PIO0_11 R/W IOCON_R_PIO1_0 R/W IOCON_R_PIO1_1 R/W IOCON_R_PIO1_2 R/W IOCON_PIO3_0 R/W IOCON_PIO3_1 R/W IOCON_PIO2_3 R/W IOCON_SWDIO_PIO1_3 R/W IOCON_PIO1_4 R/W IOCON_PIO1_11 R/W IOCON_PIO3_2 R/W IOCON_PIO1_5 R/W IOCON_PIO1_6 R/W IOCON_PIO1_7 R/W UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 105
... NXP Semiconductors Table 103. Register overview: I/O configuration (base address 0x4004 4000) Name Access IOCON_PIO3_3 R/W IOCON_SCK0_LOC R/W IOCON_DSR_LOC R/W IOCON_DCD_LOC R/W IOCON_RI_LOC R/W IOCON_CT16B0_CAP0_LOC R/W IOCON_SCK1_LOC R/W IOCON_MISO1_LOC R/W IOCON_MOSI1_LOC R/W IOCON_CT32B0_CAP0_LOC R/W IOCON_RXD_LOC R/W Table 104. I/O configuration registers ordered by port number Port pin PIO0_0 PIO0_1 PIO0_2 PIO0_3 PIO0_4 PIO0_5 PIO0_6 PIO0_7 ...
Page 106
... NXP Semiconductors Table 104. I/O configuration registers ordered by port number Port pin PIO1_10 PIO1_11 PIO2_0 PIO2_1 PIO2_2 PIO2_3 PIO2_4 PIO2_5 PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10 PIO2_11 PIO3_0 PIO3_1 PIO3_2 PIO3_3 PIO3_4 PIO3_5 8.4.1 IOCON_PIO2_6 Table 105. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description ...
Page 107
... NXP Semiconductors Table 105. IOCON_PIO2_6 register (IOCON_PIO2_6, address 0x4004 4000) bit description Bit Symbol 10 OD 31:11 - 8.4.2 IOCON_PIO2_0 Table 106. IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.3 IOCON_PIO_RESET_PIO0_0 Table 107. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) ...
Page 108
... NXP Semiconductors Table 107. IOCON_RESET_PIO0_0 register (IOCON_RESET_PIO0_0, address 0x4004 400C) Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 8.4.4 IOCON_PIO0_1 Table 108. IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) bit description ...
Page 109
... NXP Semiconductors 8.4.5 IOCON_PIO1_8 Table 109. IOCON_PIO1_8 register (IOCON_PIO1_8, address 0x4004 4014) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.6 IOCON_PIO0_2 Table 110. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 110
... NXP Semiconductors Table 110. IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description Bit Symbol 10 OD 31:11 - 8.4.7 IOCON_PIO2_7 Table 111. IOCON_PIO2_7 register (IOCON_PIO2_7, address 0x4004 4020) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.8 IOCON_PIO2_8 Table 112. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description ...
Page 111
... NXP Semiconductors Table 112. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 8.4.9 IOCON_PIO2_1 Table 113. IOCON_PIO2_1 register (IOCON_PIO2_1, address 0x4004 4028) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 112
... NXP Semiconductors 8.4.10 IOCON_PIO0_3 Table 114. IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.11 IOCON_PIO0_4 Table 115. IOCON_PIO0_4 register (IOCON_PIO0_4, address 0x4004 4030) bit description Bit Symbol 2:0 FUNC 7:3 9:8 I2CMODE 31:10 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 113
... NXP Semiconductors 8.4.12 IOCON_PIO0_5 Table 116. IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description Bit Symbol 2:0 FUNC 7:3 9:8 I2CMODE 31:10 - 8.4.13 IOCON_PIO1_9 Remark: See Table 117. IOCON_PIO1_9 register (IOCON_PIO1_9, address 0x4004 4038) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.14 IOCON_PIO3_4 Remark: See UM10398 User manual ...
Page 114
... NXP Semiconductors Table 118. IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.15 IOCON_PIO2_4 Remark: See Table 119. IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 115
... NXP Semiconductors Table 119. IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description Bit Symbol 10 OD 31:11 - 8.4.16 IOCON_PIO2_5 Remark: See Table 120. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.17 IOCON_PIO3_5 Remark: See Table 121. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description ...
Page 116
... NXP Semiconductors Table 121. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 8.4.18 IOCON_PIO0_6 Table 122. IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 117
... NXP Semiconductors 8.4.19 IOCON_PIO0_7 Table 123. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.20 IOCON_PIO2_9 Remark: See Table 124. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 118
... NXP Semiconductors Table 124. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description Bit Symbol 10 OD 31:11 - 8.4.21 IOCON_PIO2_10 Table 125. IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.22 IOCON_PIO2_2 Table 126. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description ...
Page 119
... NXP Semiconductors Table 126. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description Bit Symbol 5 HYS 9 31:11 - 8.4.23 IOCON_PIO0_8 Table 127. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.24 IOCON_PIO0_9 Table 128. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description ...
Page 120
... NXP Semiconductors Table 128. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 8.4.25 IOCON_SWCLK_PIO0_10 Table 129. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004 Bit Symbol Value 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) Value ...
Page 121
... NXP Semiconductors 8.4.26 IOCON_PIO1_10 Table 130. IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - 8.4.27 IOCON_PIO2_11 Table 131. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description Bit Symbol 2:0 FUNC 4:3 MODE UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 122
... NXP Semiconductors Table 131. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description Bit Symbol 5 HYS 9 31:11 - 8.4.28 IOCON_R_PIO0_11 Table 132. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 123
... NXP Semiconductors 8.4.29 IOCON_R_PIO1_0 Table 133. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - 8.4.30 IOCON_R_PIO1_1 Table 134. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit Bit Symbol 2:0 FUNC UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 124
... NXP Semiconductors Table 134. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit Bit Symbol 4:3 MODE 5 HYS ADMODE 9 31:11 - 8.4.31 IOCON_R_PIO1_2 Table 135. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) description … ...
Page 125
... NXP Semiconductors Table 135. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit Bit Symbol 7 ADMODE 9 31:11 - 8.4.32 IOCON_PIO3_0 Table 136. IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) description … ...
Page 126
... NXP Semiconductors 8.4.33 IOCON_PIO3_1 Table 137. IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.34 IOCON_PIO2_3 Table 138. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 127
... NXP Semiconductors Table 138. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description Bit Symbol 10 OD 31:11 - 8.4.35 IOCON_SWDIO_PIO1_3 Table 139. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) Value Description Selects pseudo open-drain mode ...
Page 128
... NXP Semiconductors 8.4.36 IOCON_PIO1_4 Table 140. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 9 31:11 - 8.4.37 IOCON_PIO1_11 Table 141. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description Bit Symbol 2:0 FUNC 4:3 MODE UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 129
... NXP Semiconductors Table 141. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description Bit Symbol 5 HYS ADMODE 9 31:11 - 8.4.38 IOCON_PIO3_2 Table 142. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 130
... NXP Semiconductors 8.4.39 IOCON_PIO1_5 Table 143. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.40 IOCON_PIO1_6 Table 144. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9:6 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) ...
Page 131
... NXP Semiconductors Table 144. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description Bit Symbol 10 OD 31:11 - 8.4.41 IOCON_PIO1_7 Table 145. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 9 31:11 - 8.4.42 IOCON_PIO3_3 Table 146. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description ...
Page 132
... NXP Semiconductors Table 146. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description Bit Symbol 4:3 MODE 5 HYS 9 31:11 - 8.4.43 IOCON_SCK0_LOC Table 147. IOCON SCK0 location register (IOCON_SCK0_LOC, address 0x4004 40B0) bit Bit Symbol 1:0 SCKLOC 31:2 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) Value ...
Page 133
... NXP Semiconductors 8.4.44 IOCON_DSR_LOC Table 148. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit Bit Symbol 1:0 DSRLOC 31:2 - 8.4.45 IOCON_DCD_LOC Table 149. IOCON DCD location register (IOCON_DCD_LOC, address 0x4004 40B8) bit Bit Symbol 1:0 DCDLOC 31:2 - 8.4.46 IOCON_RI_LOC Table 150. IOCON RI location register (IOCON_RI_LOC, address 0x4004 40BC) bit ...
Page 134
... NXP Semiconductors 8.4.47 IOCON_SSEL1_LOC Table 151. IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) bit Bit Symbol 1:0 SSEL1LOC 31:2 - 8.4.48 IOCON_CT16B0_CAP0_LOC Table 152. IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address Bit Symbol 1:0 CT16B0_CAP0LOC 31:2 - 8.4.49 IOCON_SCK1_LOC Table 153. IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) bit ...
Page 135
... NXP Semiconductors 8.4.50 IOCON_MISO1_LOC Table 154. IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) bit Bit Symbol 1:0 MISO1LOC 31:2 - 8.4.51 IOCON_MOSI1_LOC Table 155. IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) bit Bit Symbol 1:0 MOSI1LOC 31:2 - 8.4.52 IOCON_CT32B0_CAP0_LOC Table 156. IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address ...
Page 136
... NXP Semiconductors 8.4.53 IOCON_RXD_LOC Table 157. IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) bit Bit Symbol 1:0 RXDLOC 31:2 - UM10398 User manual Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG) description Value Description Selects pin location for the RXD function. 0x0 Selects RXD function in pin location ...
Page 137
UM10398 Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C, and LPC1100L series, HVQFN/LQFP packages) Rev. 12 — 24 September 2012 9.1 How to read this chapter Remark: This chapter applies to parts in the LPC1100, LPC1100C, and LPC1100L series for LQFP ...
Page 138
... NXP Semiconductors 9.2 LPC111x Pin configuration PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V SS XTALIN XTALOUT V DD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 10 11 PIO2_7 PIO2_8 12 Fig 16. Pin configuration LQFP48 package UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C LPC1113FBD48/301 LPC1113FBD48/302 7 LPC1114FBD48/301 8 LPC1114FBD48/302 9 All information provided in this document is subject to legal disclaimers. ...
Page 139
... NXP Semiconductors terminal 1 index area PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALIN XTALOUT PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 17. Pin configuration HVQFN33 package Fig 18. Pin configuration HVQFN24 package UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C R/PIO1_2/AD3/CT32B1_MAT1 2 23 R/PIO1_1/AD2/CT32B1_MAT0 3 22 R/PIO1_0/AD1/CT32B1_CAP0 4 21 R/PIO0_11/AD0/CT32B0_MAT3 5 20 PIO1_10/AD6/CT16B1_MAT1 ...
Page 140
... NXP Semiconductors 9.3 LPC11Cxx Pin configuration PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V SS XTALIN XTALOUT V DD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 10 11 PIO2_7 PIO2_8 12 Fig 19. Pin configuration LQFP48 package UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C LPC11C12FBD48/301 LPC11C14FBD48/301 All information provided in this document is subject to legal disclaimers. ...
Page 141
... NXP Semiconductors PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V SS XTALIN XTALOUT V DD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 10 11 PIO2_7 PIO2_8 12 Fig 20. Pin configuration (LPC11C22/C24) UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C LPC11C22FBD48/301 LPC11C24FBD48/301 All information provided in this document is subject to legal disclaimers. ...
Page 142
... NXP Semiconductors 9.4 LPC11D14 Pin configuration 1 PIO1_7 PIO3_3 2 n. PIO2_6 5 PIO2_0 RESET/PIO0_0 6 PIO0_1 XTALIN XTALOUT PIO1_8 13 PIO0_2 PIO2_7 14 PIO2_8 15 16 PIO2_1 17 PIO0_3 PIO0_4 18 PIO0_5 19 20 PIO1_9 21 PIO3_4 PIO2_4 22 PIO2_5 23 24 PIO3_5 25 PIO0_6 Fig 21. Pin configuration LQFP100 package UM10398 ...
Page 143
... NXP Semiconductors 9.5 LPC111x/LPC11Cxx Pin description Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package) Symbol Pin PIO0_0 to PIO0_11 [1][2] RESET/PIO0_0 3 [3][2] PIO0_1/CLKOUT/ 4 CT32B0_MAT2 [3][2] PIO0_2/SSEL0/ 10 CT16B0_CAP0 [3][2] PIO0_3 14 [4][2] PIO0_4/SCL 15 [4][2] PIO0_5/SDA 16 [3][2] PIO0_6/SCK0 22 [3][2] PIO0_7/CTS 23 [3][2] PIO0_8/MISO0/ 27 CT16B0_MAT0 [3][2] PIO0_9/MOSI0/ 28 CT16B0_MAT1 [3][2] SWCLK/PIO0_10/ 29 SCK0/CT16B0_MAT2 UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C, ...
Page 144
... NXP Semiconductors Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package) Symbol Pin [5][2] R/PIO0_11/ 32 AD0/CT32B0_MAT3 PIO1_0 to PIO1_11 [5][2] R/PIO1_0/ 33 AD1/CT32B1_CAP0 [5] R/PIO1_1/ 34 AD2/CT32B1_MAT0 [5] R/PIO1_2/ 35 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/AD4/ 39 CT32B1_MAT2 [5] PIO1_4/AD5/ 40 CT32B1_MAT3/WAKEUP [3] PIO1_5/RTS/ 45 CT32B0_CAP0 [3] PIO1_6/RXD/ 46 CT32B0_MAT0 [3] PIO1_7/TXD/ 47 CT32B0_MAT1 [3] PIO1_8/CT16B1_CAP0 9 [3] PIO1_9/CT16B1_MAT0 17 UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C, ...
Page 145
... NXP Semiconductors Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package) Symbol Pin [5] PIO1_10/AD6/ 30 CT16B1_MAT1 [5] PIO1_11/AD7 42 PIO2_0 to PIO2_11 [3] PIO2_0/DTR/SSEL1 2 [3] PIO2_1/DSR/SCK1 13 [3] PIO2_2/DCD/MISO1 26 [3] PIO2_3/RI/MOSI1 38 [3] PIO2_4 19 [3] PIO2_4 18 [3] PIO2_5 20 [3] PIO2_5 21 [3] PIO2_6 1 [3] PIO2_7 11 [3] PIO2_8 ...
Page 146
... NXP Semiconductors Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package) Symbol Pin [3] PIO3_3/RI 48 [3] PIO3_4 18 [3] PIO3_5 21 [6] CAN_RXD 19 [6] CAN_TXD [7] XTALIN 6 [7] XTALOUT [ tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
Page 147
... NXP Semiconductors Table 160. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin PIO0_0 to PIO0_11 [1][2] RESET/PIO0_0 2 [3][2] PIO0_1/CLKOUT/ 3 CT32B0_MAT2 [3][2] PIO0_2/SSEL0/ 8 CT16B0_CAP0 [3][2] PIO0_3 9 [4][2] PIO0_4/SCL 10 [4][2] PIO0_5/SDA 11 [3][2] PIO0_6/SCK0 15 [3][2] PIO0_7/CTS 16 [3][2] PIO0_8/MISO0/ 17 CT16B0_MAT0 [3][2] PIO0_9/MOSI0/ 18 CT16B0_MAT1 [3][2] SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 [5][2] R/PIO0_11/AD0/ 21 CT32B0_MAT3 PIO1_0 to PIO1_11 UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C, ...
Page 148
... NXP Semiconductors Table 160. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin [5][2] R/PIO1_0/AD1/ 22 CT32B1_CAP0 [5] R/PIO1_1/AD2/ 23 CT32B1_MAT0 [5] R/PIO1_2/AD3/ 24 CT32B1_MAT1 [5] SWDIO/PIO1_3/AD4/ 25 CT32B1_MAT2 [5] PIO1_4/AD5/ 26 CT32B1_MAT3/WAKEUP [3] PIO1_5/RTS/ 30 CT32B0_CAP0 [3] PIO1_6/RXD/ 31 CT32B0_MAT0 [3] PIO1_7/TXD/ 32 CT32B0_MAT1 [3] PIO1_8/CT16B1_CAP0 7 [3] PIO1_9/CT16B1_MAT0 12 [5] PIO1_10/AD6/ 20 CT16B1_MAT1 [5] PIO1_11/AD7 27 UM10398 User manual Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C, ...
Page 149
... NXP Semiconductors Table 160. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin PIO2_0 [3] PIO2_0/DTR 1 PIO3_0 to PIO3_5 [3] PIO3_2 28 [3] PIO3_4 13 [3] PIO3_5 [6] XTALIN 4 [6] XTALOUT [ tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
Page 150
... NXP Semiconductors Table 161. LPC1112FHN24 Pin description table (HVQFN24 package) Symbol HVQFN Start pin logic input [4] PIO0_4/SCL 8 yes [4] PIO0_5/SDA 9 yes [3] PIO0_6/SCK0 10 yes [3] PIO0_7/CTS 11 yes [3] PIO0_8/MISO0/ 12 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 13 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 14 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/ 15 yes AD0/CT32B0_MAT3 [5] R/PIO1_0/ 16 yes AD1/CT32B1_CAP0 [5] R/PIO1_1/ ...
Page 151
... NXP Semiconductors Table 161. LPC1112FHN24 Pin description table (HVQFN24 package) Symbol HVQFN Start pin logic input [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [7] XTALIN [1] Pin state at reset for default function Input ...
Page 152
... NXP Semiconductors Table 162. LPC11C24/C22 pin description table (LQFP48 package) Symbol Pin Type PIO0_0 to PIO0_11 [1] RESET/PIO0_0 3 I I/O [3] PIO0_1/CLKOUT/ 4 I/O CT32B0_MAT2 O O [3] PIO0_2/SSEL0/ 10 I/O CT16B0_CAP0 I/O I [3] PIO0_3 14 I/O [4] PIO0_4/SCL 15 I/O I/O [4] PIO0_5/SDA 16 I/O I/O [3] PIO0_6/SCK0 23 I/O I/O [3] PIO0_7/CTS 24 I/O I [3] PIO0_8/MISO0/ 27 I/O CT16B0_MAT0 I/O O [3] PIO0_9/MOSI0/ 28 I/O CT16B0_MAT1 I/O O [3] SWCLK/PIO0_10 SCK0/ ...
Page 153
... NXP Semiconductors Table 162. LPC11C24/C22 pin description table (LQFP48 package) Symbol Pin Type PIO1_0 to PIO1_11 [5] R/PIO1_0/AD1 CT32B1_CAP0 I [5] - R/PIO1_1/AD2/ 34 CT32B1_MAT0 I [5] R/PIO1_2/AD3 CT32B1_MAT1 I [5] SWDIO/PIO1_3/ 39 I/O AD4/ I/O CT32B1_MAT2 I O [5] PIO1_4/AD5/ 40 I/O CT32B1_MAT3/ I WAKEUP O I [3] PIO1_5/RTS/ 45 I/O CT32B0_CAP0 O I [3] PIO1_6/RXD/ 46 I/O CT32B0_MAT0 I O [3] PIO1_7/TXD/ 47 I/O CT32B0_MAT1 O O [3] ...
Page 154
... NXP Semiconductors Table 162. LPC11C24/C22 pin description table (LQFP48 package) Symbol Pin Type PIO2_0 to PIO2_11 [3] PIO2_0/DTR/ 2 I/O SSEL1 I/O I/O [3] PIO2_1/DSR/SCK1 13 I/O I I/O [3] PIO2_2/DCD/ 26 I/O MISO1 I I/O [3] PIO2_3/RI/MOSI1 38 I/O I I/O [3] PIO2_6 1 I/O [3] PIO2_7 11 I/O [3] PIO2_8 12 I/O [3] PIO2_10 25 I/O [3] PIO2_11/SCK0 31 I/O I/O PIO3_0 to PIO3_3 [3] PIO3_0/DTR 36 I/O O [3] PIO3_1/DSR 37 I/O I [3] PIO3_2/DCD ...
Page 155
... NXP Semiconductors Table 162. LPC11C24/C22 pin description table (LQFP48 package) Symbol Pin Type [7] XTALIN 6 I [7] XTALOUT [ tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. ...
Page 156
... NXP Semiconductors Table 163. LPC11D14 pin description table (LQFP100 package) Symbol Pin Start logic input [4] PIO0_5/SDA 19 yes [3] PIO0_6/SCK0 25 yes [3] PIO0_7/CTS 26 yes [3] PIO0_8/MISO0/ 81 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 82 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 83 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/ 86 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/ 87 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 ...
Page 157
... NXP Semiconductors Table 163. LPC11D14 pin description table (LQFP100 package) Symbol Pin Start logic input [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD/ 100 no CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0 [5] PIO1_10/AD6/ ...
Page 158
... NXP Semiconductors Table 163. LPC11D14 pin description table (LQFP100 package) Symbol Pin Start logic input [3] PIO2_0/DTR/SSEL1 5 no [3] PIO2_1/DSR/SCK1 16 no [3] PIO2_2/DCD/MISO1 80 no [3] PIO2_3/RI/MOSI1 92 no [3] PIO2_4 22 no [3] PIO2_5 23 no [3] PIO2_6 4 no [3] PIO2_7 14 no [3] PIO2_8 15 no [3] PIO2_9 27 no [3] PIO2_10 28 no [3] PIO2_11/SCK0 85 no PIO3_0 to PIO3_5 ...
Page 159
... NXP Semiconductors Table 163. LPC11D14 pin description table (LQFP100 package) Symbol Pin Start logic input LCD display pins S10 56 - S11 57 - S12 58 - S13 59 - S14 60 - S15 61 - S16 62 - S17 63 - S18 64 - S19 65 - S20 66 - S21 67 - S22 ...
Page 160
... NXP Semiconductors Table 163. LPC11D14 pin description table (LQFP100 package) Symbol Pin Start logic input S38 33 - S39 34 - BP0 42 - BP1 44 - BP2 43 - BP3 45 - LCD_SDA 35 - LCD_SCL 36 - SYNC 37 - CLK DD(LCD SS(LCD LCD n. [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full inactive, no pull-up/down enabled ...
Page 161
UM10398 Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP, SO packages) Rev. 12 — 24 September 2012 10.1 How to read this chapter This chapter describes the small pin packages for the LPC111x parts in TSSOP, DIP, and SO ...
Page 162
... NXP Semiconductors PIO0_8/MISO0/CT16B0_MAT0 PIO0_9/MOSI0/CT16B0_MAT1 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 R/PIO1_0/AD1/CT32B1_CAP0 R/PIO1_1/AD2/CT32B1_MAT0 R/PIO1_2/AD3/CT32B1_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 Fig 23. Pin configuration TSSOP20 package with I Table 165. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I Symbol Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 17 yes [3] PIO0_1/CLKOUT/ 18 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 19 yes CT16B0_CAP0 ...
Page 163
... NXP Semiconductors Table 165. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I Symbol Start logic input [3] PIO0_9/MOSI0/ 2 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 3 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/ 4 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_7 [5] R/PIO1_0/ 7 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 AD2/CT32B1_MAT0 [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 ...
Page 164
... NXP Semiconductors Table 165. LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I Symbol Start logic input [6] XTALIN 14 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full V no pull-up/down enabled. ...
Page 165
... NXP Semiconductors Table 166. LPC1112 pin description table (TSSOP20 with V Symbol Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 17 yes [3] PIO0_1/CLKOUT/ 18 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 19 yes CT16B0_CAP0 [3] PIO0_3 20 yes [3] PIO0_8/MISO0/ 1 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 2 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 3 yes SCK0/ CT16B0_MAT2 [4] R/PIO0_11/ 4 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_7 ...
Page 166
... NXP Semiconductors Table 166. LPC1112 pin description table (TSSOP20 with V Symbol Start logic input [4] R/PIO1_0/ 7 yes AD1/CT32B1_CAP0 [4] R/PIO1_1 AD2/CT32B1_MAT0 [4] R/PIO1_2 AD3/CT32B1_MAT1 [4] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 DDA [5] XTALIN 14 - [5] XTALOUT ...
Page 167
... NXP Semiconductors [ tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. [5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise) ...
Page 168
... NXP Semiconductors Table 167. LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 23 yes [3] PIO0_1/CLKOUT/ 24 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 25 yes CT16B0_CAP0 [3] PIO0_3 26 yes [4] PIO0_4/SCL 27 yes [4] PIO0_5/SDA 5 yes [3] PIO0_6/SCK0 6 yes [3] PIO0_7/CTS 28 yes [3] PIO0_8/MISO0/ 1 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 2 yes ...
Page 169
... NXP Semiconductors Table 167. LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol Start logic input [5] R/PIO0_11/ 4 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_9 [5] R/PIO1_0/ 9 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 AD2/CT32B1_MAT0 [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 UM10398 ...
Page 170
... NXP Semiconductors Table 167. LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol Start logic input [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0 DDA [6] XTALIN 20 - [6] XTALOUT SSA [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full V no pull-up/down enabled ...
Page 171
UM10398 Chapter 11: LPC111x Pin configuration (LPC1100XL series, HVQFN/LQFP packages) Rev. 12 — 24 September 2012 11.1 How to read this chapter Remark: This chapter applies to parts in the LPC1100XL series for LQFP and HVQFN packages. The LPC111x are ...
Page 172
... NXP Semiconductors 11.2 LPC111x Pin configuration PIO2_6/CT32B0_MAT1 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V SS XTALIN XTALOUT V DD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 10 11 PIO2_7/CT32B0_MAT2/RXD PIO2_8/CT32B0_MAT3/TXD 12 Fig 27. Pin configuration LQFP48 package UM10398 User manual Chapter 11: LPC111x Pin configuration (LPC1100XL series LPC1113FBD48/303 6 LPC1114FBD48/303 LPC1114FBD48/323 7 LPC1114FBD48/333 8 LPC1115FBD48/303 9 All information provided in this document is subject to legal disclaimers. ...
Page 173
... NXP Semiconductors terminal 1 index area PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALIN XTALOUT PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 28. Pin configuration HVQFN33 package 11.3 LPC1100XL Pin description Table 169. LPC1113/14/15XL pin description table (LQFP48 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 3 yes UM10398 User manual ...
Page 174
... NXP Semiconductors Table 169. LPC1113/14/15XL pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO0_1/CLKOUT/ 4 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 10 yes CT16B0_CAP0 [3] PIO0_3 14 yes [4] PIO0_4/SCL 15 yes [4] PIO0_5/SDA 16 yes [3] PIO0_6/SCK0 22 yes [3] PIO0_7/CTS 23 yes [3] PIO0_8/MISO0/ 27 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 28 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 29 yes SCK0/ ...
Page 175
... NXP Semiconductors Table 169. LPC1113/14/15XL pin description table (LQFP48 package) Symbol Pin Start logic input [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 AD2/CT32B1_MAT0 [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 ...
Page 176
... NXP Semiconductors Table 169. LPC1113/14/15XL pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO1_9 CT16B1_MAT0/ MOSI1 [5] PIO1_10/AD6 CT16B1_MAT1/ MISO1 [5] PIO1_11/AD7 CT32B1_CAP1 PIO2_0 to PIO2_11 [3] PIO2_0/DTR/SSEL1 2 no [3] PIO2_1/DSR/SCK1 13 no [3] PIO2_2/DCD/MISO1 26 no [3] PIO2_3/RI/MOSI1 38 no [3] PIO2_4 CT16B1_MAT1/ ...
Page 177
... NXP Semiconductors Table 169. LPC1113/14/15XL pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO2_9 CT32B0_CAP0 [3] PIO2_10 25 no [3] PIO2_11/SCK0 CT32B0_CAP1 PIO3_0 to PIO3_5 [3] PIO3_0/DTR CT16B0_MAT0/TXD [3] PIO3_1/DSR CT16B0_MAT1/RXD [3] PIO3_2/DCD CT16B0_MAT2/ SCK1 [ PIO3_3/RI/ CT16B0_CAP0 [3] PIO3_4 ...
Page 178
... NXP Semiconductors [ tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis [4] I C-bus pads compliant with the I C-bus specification for I [ tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. ...
Page 179
... NXP Semiconductors Table 170. LPC1111/12/13/14XL pin description table (HVQFN33 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 2 yes [3] PIO0_1/CLKOUT/ 3 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 8 yes CT16B0_CAP0 [3] PIO0_3 9 yes [4] PIO0_4/SCL 10 yes [4] PIO0_5/SDA 11 yes [3] PIO0_6/SCK0 15 yes [3] PIO0_7/CTS 16 yes [3] PIO0_8/MISO0/ 17 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 18 yes ...
Page 180
... NXP Semiconductors Table 170. LPC1111/12/13/14XL pin description table (HVQFN33 package) Symbol Pin Start logic input [5] R/PIO0_11/AD0/ 21 yes CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/AD1/ 22 yes CT32B1_CAP0 [5] R/PIO1_1/AD2 CT32B1_MAT0 [5] R/PIO1_2/AD3 CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD/ ...
Page 181
... NXP Semiconductors Table 170. LPC1111/12/13/14XL pin description table (HVQFN33 package) Symbol Pin Start logic input [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0/ MOSI [5] PIO1_10/AD6 CT16B1_MAT1/ MISO [5] PIO1_11/AD7 CT32B1_CAP1 PIO2_0 [3] PIO2_0/DTR/SSEL1 1 no PIO3_0 to PIO3_5 [3] PIO3_2 CT16B0_MAT2/ ...
Page 182
... NXP Semiconductors Table 170. LPC1111/12/13/14XL pin description table (HVQFN33 package) Symbol Pin Start logic input [6] XTALIN 4 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full inactive, no pull-up/down enabled. ...
Page 183
UM10398 Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO) Rev. 12 — 24 September 2012 12.1 How to read this chapter The number of GPIO pins available on each port depends on the LPC111x/LPC11Cxx part and the package. See Table 171. ...
Page 184
... NXP Semiconductors • All GPIO pins are inputs by default. • Reading and writing of data registers are masked by address bits 13:2. 12.3 Register description Each GPIO register can bits wide and can be read or written using word or half-word operations at word addresses. Table 172. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000; ...
Page 185
... NXP Semiconductors • pin is configured as GPIO input, a write to the GPIOnDATA register has no effect on the pin level. A read returns the current state of the pin. • pin is configured as GPIO output, the current value of GPIOnDATA register is driven to the pin. This value can be a result of writing to the GPIOnDATA register can reflect the previous state of the pin if the pin is switched to GPIO output from GPIO input or another digital function ...
Page 186
... NXP Semiconductors 12.3.4 GPIO interrupt both edges sense register Table 176. GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 Bit Symbol Description 11:0 IBE 31:12 - 12.3.5 GPIO interrupt event register Table 177. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 Bit Symbol 11:0 IEV ...
Page 187
... NXP Semiconductors Table 179. GPIOnRIS register (GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003 Bit Symbol Description 11:0 RAWST Raw interrupt status ( 11). 31:12 - 12.3.8 GPIO masked interrupt status register Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input pins has been generated or that the interrupt is masked ...
Page 188
... NXP Semiconductors 12.4 Functional description 12.4.1 Write/read data operation In order for software to be able to set GPIO bits without affecting any other pins in a single write operation, bits [13: 14-bit wide address bus are used to create a 12-bit wide mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA bits masked by 1 are affected by read and write operations ...
Page 189
... NXP Semiconductors Read operation If the address bit associated with the GPIO data bit is HIGH, the value is read. If the address bit is LOW, the GPIO data bit is read as 0. Reading a port DATA register yields the state of port pins 11:0 ANDed with address bits 13:2. Fig 30. Masked read operation ...
Page 190
UM10398 Chapter 13: LPC111x/LPC11Cxx UART Rev. 12 — 24 September 2012 13.1 How to read this chapter The UART block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The DSR, DCD, and RI modem signals are fully pinned out ...
Page 191
... NXP Semiconductors 13.4 Pin description Table 182. UART pin description Pin Type RXD Input TXD Output Serial Output. Serial transmit data. RTS Output Request To Send. RS-485 direction control pin. DTR Output Data Terminal Ready. [1] DSR Input CTS Input [1] DCD Input [1] RI Input [1] LQFP48 packages only ...
Page 192
... NXP Semiconductors Table 183. Register overview: UART (base address: 0x4000 8000) Name Access Address offset U0LCR R/W 0x00C U0MCR R/W 0x010 U0LSR RO 0x014 U0MSR RO 0x018 U0SCR R/W 0x01C U0ACR R/W 0x020 - - 0x024 U0FDR R/W 0x028 - - 0x02C U0TER R/W 0x030 - - 0x034 - 0x048 U0RS485CTRL R/W 0x04C U0RS485ADR R/W 0x050 MATCH U0RS485DLY ...
Page 193
... NXP Semiconductors 13.5.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “ ...
Page 194
... NXP Semiconductors Table 186. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1) Bit Symbol 7:0 DLLSB 31:8 - Table 187. UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when Bit Symbol 7:0 DLMSB 31:8 - 13.5.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when DLAB = 0) The U0IER is used to enable the four UART interrupt sources ...
Page 195
... NXP Semiconductors Table 188. UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit Bit Symbol 9 ABTOINTEN 31:10 - 13.5.5 UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only) U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during a U0IIR access interrupt occurs during a U0IIR access, the interrupt is recorded for the next U0IIR access ...
Page 196
... NXP Semiconductors If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the IntStatus non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt ...
Page 197
... NXP Semiconductors Table 190. UART Interrupt Handling U0IIR[3:0] [1] value 1100 0010 0000 [1] Values “0000”, “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved. [2] For details see [3] For details see Read Only)” ...
Page 198
... NXP Semiconductors Table 191. UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit Bit Symbol 0 FIFOEN 1 RXFIFORES 2 TXFIFORES 3 - 5:4 - 7:6 RXTL 31:8 - 13.5.7 UART Line Control Register (U0LCR - 0x4000 800C) The U0LCR determines the format of the data character that transmitted or received. Table 192. UART Line Control Register (U0LCR - address 0x4000 800C) bit description ...
Page 199
... NXP Semiconductors Table 192. UART Line Control Register (U0LCR - address 0x4000 800C) bit description Bit Symbol Value Description DLAB 31 13.5.8 UART Modem Control Register The U0MCR enables the modem loopback mode and controls the modem output signals. Table 193. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description ...
Page 200
... NXP Semiconductors Table 193. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description Bit Symbol 4 LMS RTSEN 7 CTSEN 31:8 - 13.5.8.1 Auto-flow control If auto-RTS mode is enabled the UART‘s receiver FIFO hardware controls the RTS output of the UART. If the auto-CTS mode is enabled the UART‘s U0TSR hardware will only start transmitting if the CTS input signal is asserted ...