MPC8536ECVTATLA Freescale Semiconductor, MPC8536ECVTATLA Datasheet - Page 27

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MPC8536ECVTATLA

Manufacturer Part Number
MPC8536ECVTATLA
Description
Microprocessors - MPU 8536 ENCRYPTED
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8536ECVTATLA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
250 MHz
Program Memory Size
32 KB
Data Ram Size
512 KB
Interface Type
I2C, USB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
0 C to + 105 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-783
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
Nap (W)
Sleep (W)
Deep Sleep
(W)
Notes:
1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and
2. Typical power is an average value measured at the nominal recommended core voltage (V
3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (V
4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (V
6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the
7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of
8. Maximum operating junction temperature (see
9. Platform power is the power supplied to all the
See
Freescale Semiconductor
Power Mode
configurations. The values do not include power dissipation for I/O supplies.
(see
at maximum operating junction temperature (see
L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy.
at maximum operating junction temperature (see
mean power measured with only external interrupts enabled and DDR in self refresh.
devices.
Section 2.23.6.1, “SYSCLK to Platform Frequency
Table
3) while running the Dhrystone benchmark.
Frequen
(MHz)
Core
1250
cy
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Frequen
(MHz)
CCB
500
cy
Frequen
(MHz)
DDR
500
cy
Table 5. Power Dissipation (continued)
Platfor
V
1.0
(V)
m
DD
Table
V
DD_PLAT
Table
Table
3) for Commercial Tier is 90
Options,” for the full range of CCB frequencies that the chip supports.
Core
V
1.0
(V)
3) while running a smoke test which includes an entirely
3) while running the Dhrystone benchmark.
DD
pins.
Junction
Tempera
ture
(°C)
105
/ 90
65
35
mean
2.2
1.6
0.8
0.8
Core Power
0
7
0
C, for Industrial Tier is 105
5
5.3/4.4
4.4/3.6
Max
2.4
1.6
1.6
0
DD
) and 65°C junction temperature
mean
Platform Power
Electrical Characteristics
1.7
1.5
1.5
1.1
0.6
7
5.0/4.0
5.0/4.0
Max
2.1
2.1
1.7
1.2
0
C.
9
Notes
1, 3, 8
1, 4, 8
1, 6
1
1
1
1
DD
DD
27
)
)

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