MPC8536ECVTATLA Freescale Semiconductor, MPC8536ECVTATLA Datasheet - Page 86

• Manufacturer Part Number: MPC8536ECVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536ECVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

All values refer to V
Electrical Characteristics
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal)
3. The maximum t
4. C
This figure provides the AC test load for the I
This figure shows the AC timing diagram for the I
86
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the
chip acts as the I
are balanced, the chip would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output
delay time is not a concern. For details of the I
for SCL (AN2919). Note that the I
B
SDA
= capacitance of one bus line in pF.
SCL
S
IH
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(min) and V
2
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
t
C bus master while transmitting, the chip drives both SCL and SDA. As long as the load on SCL and SDA
I2CF
t
I2CL
t
I2SXKL
has only to be met if the chip does not stretch the LOW period (t
Parameter
Output
IL
(max) levels (see
Table 64. I
2
I2SXKL
I2C
C Source Clock Frequency is half of the CCB clock frequency for the chip.
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 52. I
t
I2DXKL,
symbolizes I
2
C AC Electrical Specifications (continued)
2
C.
Figure 51. I
Table
2
Z
t
C frequency calculation, refer to Determining the I
I2DVKH
0
t
2
I2OVKL
C bus.
= 50 Ω
63).
t
I2CH
2
C Bus AC Timing Diagram
2
C timing (I2) for the time that the data with respect to the start condition
t
I2SXKL
2
C AC Test Load
Symbol
t
I2KHDX
Sr
V
V
NH
NL
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
t
I2SVKH
1
t
I2KHKL
R
L
0.1 × OV
0.2 × OV
= 50 Ω
Min
1.3
DD
DD
I2CL
t
I2PVKH
I2C
OV
) of the SCL signal.
DD
t
clock reference (K) going to the
I2CR
Max
I2DVKH
/2
—
—
—
2
C Frequency Divider Ratio
Freescale Semiconductor
P
symbolizes I
I2PVKH
t
I2CF
Unit
μs
V
V
symbolizes I
S
2
C timing
I2C
Notes
—
—
—
clock
2
C