KPC8544EVTANG Freescale Semiconductor, KPC8544EVTANG Datasheet - Page 106

• Manufacturer Part Number: KPC8544EVTANG
• Description: Microprocessors - MPU PQ38K 8544E
• Manufacturer: Freescale Semiconductor

Specifications of KPC8544EVTANG

• Product Category: Microprocessors - MPU
• Rohs: yes
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: FCPBGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 5

System Design Information
21.2
Each of the PLLs listed above is provided with power through independent power supply pins
(AV
level should always be equivalent to V
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of 783 FC-PBGA the footprint, without the inductance of vias.
Figure 65
The AV
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
Figure
AV
near the AV
and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AV
to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All
traces should be kept short, wide, and direct.
106
DD
DD
DD
_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be
pins. By providing independent filters to each PLL the opportunity to cause noise injection from
_PLAT, AV
66. For maximum effectiveness, the filter circuit is placed as closely as possible to the
DD
PLL Power Supply Filtering
shows the PLL power supply filter circuit.
_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability
DD
_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by the 1-µF capacitor,
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
DD
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
SV
V
DD
_CORE, AV
DD
Figure 65. MPC8544E PLL Power Supply Filter Circuit
Figure 66. SerDes PLL Power Supply Filter Circuit
1.0 Ω
10 Ω
DD
_PCI, AV
DD
, and preferably these voltages will be derived directly from V
2.2 µF
2.2 µF
DD
1
GND
_LBIU, and AV
GND
Low ESL Surface Mount Capacitors
2.2 µF
2.2 µF
1
DD
AV
0.003 µF
_SRDS, respectively). The AV
DD
DD
pin being supplied to minimize
Figure
AV
DD
_SRDS
65, one to each of the
Freescale Semiconductor
DD
_SRDSn
DD
DD
DD