74LVC16245AEV/G NXP Semiconductors, 74LVC16245AEV/G Datasheet
74LVC16245AEV/G
Specifications of 74LVC16245AEV/G
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74LVC16245AEV/G Summary of contents
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... V tolerant; 3-state Rev. 12 — 13 February 2012 1. General description The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for direction control ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Temperature range Package 40 C to +125 C 74LVC16245ADL 74LVCH16245ADL 40 C to +125 C 74LVC16245ADGG 74LVCH16245ADGG 40 C to +125 C 74LVC16245AEV 74LVCH16245AEV 40 C to +125 C 74LVC16245ABX 74LVCH16245ABX 4. Functional diagram 1DIR 1A0 1A1 ...
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... NXP Semiconductors Fig 2. IEC logic symbol Fig 3. Bus hold circuit 74LVC_LVCH16245A Product data sheet 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin tolerant; 3-state 1OE G3 1DIR 3EN1[BA] 3EN2[AB] G6 2OE 6EN1[BA] 2DIR 6EN2[AB] 1A0 1 2 1A1 1A2 1A3 1A4 1A5 1A6 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC16245A 74LVCH16245A 1DIR 1 1B0 2 1B1 3 GND 4 1B2 5 1B3 1B4 8 1B5 9 GND 10 1B6 11 1B7 12 2B0 13 2B1 14 GND 15 2B2 16 2B3 2B4 19 2B5 20 GND 21 2B6 22 2B7 23 2DIR 24 001aad110 Fig 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) ...
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... NXP Semiconductors terminal 1 index area (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However soldered, the solder land should remain floating or be connected to GND. Fig 6. Pin configuration SOT1134-2 (HXQFN60) ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1, 24 1B0 to 1B7 11, 12 2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1OE, 2OE 48, 25 1A0 to 1A7 47, 46, 44, 43, 41, ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I bus hold LOW V BHL CC [4][5] current bus hold HIGH V BHH CC [4][5] current bus hold LOW V BHLO CC overdrive current V CC [4][ bus hold HIGH ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t disable time nOE to nAn, nBn; see dis power per input dissipation V CC capacitance [ the same as t and t ...
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... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 8. 3-state enable and disable times Table 8. Measurement points Supply voltage 0.5 V 1.2 V 0.5 1.95 V 0.5 ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 9 ...
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... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 0.65 mm ball A1 index area ball A1 1 index area DIMENSIONS (mm are the original dimensions UNIT 1 2 max. 0.3 0.7 0. 0.2 0.6 0.35 OUTLINE VERSION IEC SOT702-1 Fig 12 ...
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... NXP Semiconductors HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 0.5 mm terminal 1 index area A10 terminal 1 index area Dimensions Unit max ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVC_LVCH16245A v.12 20120213 • Modifications: 74LVC_LVCH16245A v.11 20111208 • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... V tolerant; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations ...