DAC1008D650HN/C1 NXP Semiconductors, DAC1008D650HN/C1 Datasheet - Page 52

• Manufacturer Part Number: DAC1008D650HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D650HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
Table 60.
Default settings are shown highlighted.
Table 61.
Default settings are shown highlighted.
DAC1008D650
Product data sheet
Bit
5
4
3
2
1
0
Bit
7
5 to 4
2
1 to 0
Symbol
FULL_RE_INIT
SYNC_INIT_LEVEL
-
-
FORCE_RESET_DCLK
FORCE_RESET_FCLK
Symbol
SR_CDI
CDI_MODE[1:0]
FCLK_POL
FCLK_SEL[1:0]
10.15.2.6 Page 2 bit definition detailed description
MAINCONTROL register (address 00h) bit description
JCLK_CNTRL register (address 03h) bit description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 59
All information provided in this document is subject to legal disclaimers.
Access
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Rev. 3 — 31 January 2012
for a register overview and their default values. In the following
Value
0
1
0
1
0
1
0
1
Value
0
1
00
01
10
11
0
1
00
01
10
11
2, 4 or 8 interpolating DAC with JESD204A
Description
initialization
synchronization
must be written with ’0’
must be written with ’0’
reset_fclk
Description
cdi reset
cdi mode
f
reset_dclk
f
clk
clk
quick reinitialization
full reinitialization
synchronization starts with '0'
synchronization starts with '1'
release reset_dclk
force reset_dclk
release reset_fclk
force reset_fclk
no action
soft reset cdi
cdi_mode 0 (^2 modes)
cdi_mode 1 (^4 modes)
cdi_mode 2 (^8 modes)
reserved
no action
invert polarity
dclk  2
dclk
dclk_div2; running
dclk_div2; reset dclk_div2 divider
polarity
clock source
DAC1008D650
© NXP B.V. 2012. All rights reserved.
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