M95512-DFMN6TP STMicroelectronics, M95512-DFMN6TP Datasheet - Page 18

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M95512-DFMN6TP

Manufacturer Part Number
M95512-DFMN6TP
Description
EEPROM 512Kbit Serial Bus 128kB 10MHz EEProm
Manufacturer
STMicroelectronics
Datasheet

Specifications of M95512-DFMN6TP

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Instructions
6.2
18/51
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Figure 9.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
9, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 11124 Rev 20
High Impedance
0
1
2
Instruction
M95512-W M95512-R M95512-DR M95512-DF
3
4
5
6
7
AI03750D

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