M95512-DFMN6TP STMicroelectronics, M95512-DFMN6TP Datasheet - Page 20

• Manufacturer Part Number: M95512-DFMN6TP
• Description: EEPROM 512Kbit Serial Bus 128kB 10MHz EEProm
• Manufacturer: STMicroelectronics

Specifications of M95512-DFMN6TP

• Rohs: yes

Instructions
6.3.4
6.4
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SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in
Figure 11. Write Status Register (WRSR) sequence
Status Register Write Protect
SRWD
b7
S
C
D
Q
Status Register format
0
0
1
High Impedance
Doc ID 11124 Rev 20
0
2
Instruction
3
4
Figure
5
0
6
M95512-W M95512-R M95512-DR M95512-DF
11.
7
MSB
7
8
BP1
6
9 10 11 12 13 14 15
Block Protect bits
5
Register In
4
Status
3
Write Enable Latch bit
BP0
2
1
0
WEL
Write In Progress bit
AI02282D
WIP
b0