LFE3-150EA-6LFN1156I Lattice, LFE3-150EA-6LFN1156I Datasheet - Page 2

• Manufacturer Part Number: LFE3-150EA-6LFN1156I
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN1156I

• Rohs: yes
• Factory Pack Quantity: 24

LatticeECP3 Architecture
Architecture Overview
LatticeECP3 FPGAs utilize Lattice’s third generation of cost
optimized transceivers and a low-power 65-nm process FPGA
architecture. Building on the successful LatticeECP2M
family, LatticeECP3 devices deliver high-performance SERDES
blocks, cascadable high-performance sysDSP
and sysMEM
PLLs, DDR3 memory interface, and sysIO buffers. LatticeECP3
provides a low-cost, low-power programmable solution for a
wide variety of wireless and wireline applications.
Programmable Function
Unit (PFU) Block Diagram
sysDSP Block Diagram
Routing
From
Output Registers
Input Registers
∑ ± & + ⊕
Multipliers
==
Registers
Carry Chain
Pipeline
Slice 0
ALU
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
™
Carry Chain
embedded RAM, distributed memory, sysCLOCK
Slice 3
Slice 2
Slice 1
Slice 0
Output Registers
Input Registers
FF
FF
FF
FF
FF
FF
∑ ± & + ⊕
Multipliers
Registers
==
Slice 1
Pipeline
ALU
Routing
To
™
sysMEM Config Options
LatticeECP3 EBR SRAM (Mbits)
Feedback
sysCLOCK PLL Block Diagram
, ultra-high logic
Control
Signals
Single Port
Reset
Clock
Clock
Input
16384 x 1
1024 x 18
7
6
5
4
3
2
1
0
8192 x 2
4096 x 4
2048 x 9
512 x 36
17K
Internal Feedback
™
FPGA
7Mb
UP TO
33K
Frequency
Detector /
Oscillator
Voltage
Control
Phase
Dual Port
16384 x 1
1024 x 18
8192 x 2
4096 x 4
2048 x 9
LUTs
—
67K
LatticeECP3 Block Diagram
Embedded 3.2Gbps SERDES
support PCI Express, Ethernet
(XAUI, 1GbE, SGMII), CPRI,
and 3G/HD/SD-SDI.
Programmable
Function Unit
(PFU)
perform Logic,
Arithmetic,
Distributed RAM
and Distributed
ROM functions.
sysCLOCK PLLs
& DLLs for
clock
management.
Flexible sysIO
Buffers support
LVCMOS,
HSTL, SSTL,
LVDS and more.
On-Chip
Oscillator
Duty Cycle/
Duty Trim
Duty Trim
Phase/
Divider
92K
Lock Detect
Pseudo-Dual
16384 x 1
1024 x 18
8192 x 2
4096 x 4
2048 x 9
512 x 36
Port
149K
÷3
Configuration Logic supports
dual boot, encryption and TransFR
updates.
SERDES SERDES SERDES SERDES
Dual-boot and 128-bit AES
Encryption
Sector 0
Sector 1
Pre-Engineered Source
Synchronous Interfaces
Fabric
FPGA
DDR3 (800 Mbps)
7:1 LVDS, ADC/DAC
SPI Configuration
[
[
Configuration A
Configuration B
Memory
Gearbox
Gearbox
Pre-Engineered Source
Synchronous Support
implements DDR3 at
800Mbps and generic
interfaces up to 1Gbps.
DQS/Strobe Delay & Transition Detect
4:1
4:1
& Write Clock Generation
Output Register
Register Block
(15 Flip/Flops)
Input Register
(2 Flip/Flops)
(6 Flip/Flops)
Control
Read
Data
Tri-State
Block
Block
sysMEM Embedded Block
RAM (EBR) provides 18kbit
dual port RAM.
128-bit Key
Decryption
LatticeECP3
Engine
Correction
Cascadable
sysDSP Blocks
implements
high-performance
multiplier, MAC,
wide adder
trees, and ALU
functions
efficiently.
JTAG
ISI
FPGA
Logic