LFE3-150EA-6LFN1156I Lattice, LFE3-150EA-6LFN1156I Datasheet - Page 3

• Manufacturer Part Number: LFE3-150EA-6LFN1156I
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -6 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-6LFN1156I

• Rohs: yes
• Factory Pack Quantity: 24

High-Value, Low-Power Serial
Protocol Solutions
LatticeECP3 Multi-Protocol Stack
CPRI Low Latency Option
Enhanced SMPTE Support
* CPRI Supported By Extension
Supported
PHYs
Soft IP
Embedded
SERDES
and
Physical
Coding
Sub-Layers
(PCS)
Supports commonly used Ethernet protocols (1GbE, SGMII, and XAUI),
Wireless protocols, such as CPRI, are supported by extension
Supports PCI Express and Serial RapidIO
Supports data rates for up to 3.072Gbps CPRI links
Supports multi-hop RRH applications through innovative low-latency
variation SERDES implemementation
Library of CPRI, JESD204A, SRIO, Ethernet and DSP cores and reference
designs for single-chip RF and baseband implementations
Word Aligner Variation
Any rate, any channel, any direction for SD/HD and 3G
• New x11 divider setting
• Added independent Rx clocking per channel
Truly independent Rx/Tx multi-rate support for SD/HD/3G!
RX
HD
Offset Registers
Rec Clk 3
Tx 3
Reported in
Rx 3
CDR
3G
Recovered Clock
Auto Negotiation
Des
Clock Tolerance
3G
State Machine
Compensation
GbE / SGMII*
GbE & SGMII
Synchronize
Rec Clk 2
Rx Link
8b/10b
Rx 2
Tx 2
Tx
SERDES/PCS
Offset
Rx
WA
HD
Reference Clock
148.35 MHz
10b/8b
148.5 MHz
SMPTE Divider Settings
Clock Tolerance
Compensation
Synchronize
XAUI State
DIV2: 1.485 Gbps
DIV11: 270 Mbps
XAUI PCS
Soft Logic
Alignment
DIV1: 2.97 Gbps
Machine
Channel
Rx Link
8b/10b
Rx
XAUI
Tx
PLL (x20)
LatticeECP3 SERDES
Bypassable
Fabric
Rx
Bridge
FIFO
Reference Clock
Bypassable Bridge FIFO
Domain Implementation
148.5 MHz
for Single Clock
Clock Tolerance
Tx
ff_rxi_clk
8b or 16b
Compensation
rx data
To SCI
Synchronize
Soft Logic
Alignment
PCIe PHY
Express
Framing
Channel
Rx Link
8b/10b
LTSSM
Tx
PCI
Rx
SD
FPGA Fabric
Rec Clk 1
Rx 1
Tx 1
IP Core
CPRI
3G
Clock Tolerance
State Machine
Compensation
Synchronize
User Interface
Soft Logic
Alignment
Fractional
RapidIO
RX State
Machine
Channel
Rx Link
8b/10b
Serial
Tx
IP Core
HD
Rec Clk 0
Rx
Rx 0
Tx 0
rx_clk
SD
Evaluation &
Development
Boards
To accelerate your design development,
Lattice offers several development boards
to support LatticeECP3 designs. These
boards enable you to evaluate the benefits
and capabilities of LatticeECP3 devices in
a lab setting.
multi-protocol serial protocol functionality as well
multi-rate 3G/HD/SDI and 7:1 LVDS capabilities.
cost FPGA HDR camera BOM. Features include
The LatticeECP3 Serial Protocol Board provides
The LatticeECP3 Video Protocol Board provides
Breakout options for other display interfaces are
a platform to evaluate the LatticeECP3 device's
a platform to evaluate the LatticeECP3 device's
wide-range of networking and system design
no external frame buffer, enabling the lowest
ports. It is useful for appreciating the quality
of LatticeECP3 SERDES and developing a
with PCI Express and two Gigabit Ethernet
auto-exposure, extremely low-latency and
The LatticeECP3 Versa Evaluation Board
Development Kit is an FPGA-based HDR
over HDMI/DVI output. The design needs
is the industry's lowest cost FPGA board
as DDR2 and DDR3 memory interfaces.
camera capable of supporting 1080p60
Auto White Balance, industry's fastest
The Lattice HDR-60 Video Camera
120dB High Dynamic Range.
also available.
applications.