EP4CE15M9C7N Altera Corporation, EP4CE15M9C7N Datasheet

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EP4CE15M9C7N

Manufacturer Part Number
EP4CE15M9C7N
Description
FPGA - Field Programmable Gate Array FPGA - Cyclone IV 963 LABS 165 IOs
Manufacturer
Altera Corporation
Series
Cyclone IVr
Datasheet

Specifications of EP4CE15M9C7N

Rohs
yes
Number Of Logic Blocks
963
Embedded Block Ram - Ebr
504 kbit
Number Of I/os
165
Maximum Operating Frequency
200 MHz
Operating Supply Voltage
1 V to 1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
BGA-256
Minimum Operating Temperature
0 C

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Part Number:
EP4CE15M9C7N
Manufacturer:
ALTERA
0
CYIV-51001-1.7
Cyclone IV Device Family Features
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Cyclone IV Device Handbook,
Volume 1
February 2013
February 2013
CYIV-51001-1.7
Altera’s new Cyclone
leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a
transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive
applications, enabling system designers to meet increasing bandwidth requirements
while lowering costs.
Built on an optimized low-power process, the Cyclone IV device family offers the
following two variants:
Providing power and cost savings without sacrificing performance, along with a
low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost,
small-form-factor applications in the wireless, wireline, broadcast, industrial,
consumer, and communications industries.
The Cyclone IV device family offers the following features:
Cyclone IV E—lowest power, high functionality with the lowest cost
Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125 Gbps
transceivers
1
f
Low-cost, low-power FPGA fabric:
6K to 150K logic elements
Up to 6.3 Mb of embedded memory
Up to 360 18 × 18 multipliers for DSP processing intensive applications
Protocol bridging applications for under 1.5 W total power
Cyclone IV E devices are offered in core voltage of 1.0 V and 1.2 V.
For more information, refer to the
chapter.
®
IV FPGA device family extends the Cyclone FPGA series
1. Cyclone IV FPGA Device Family
Power Requirements for Cyclone IV Devices
Overview
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Registered
9001:2008
ISO

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EP4CE15M9C7N Summary of contents

Page 1

... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice ...

Page 2

... Basic mode (up to 3.125 Gbps) ■ V-by-One (up to 3.0 Gbps) ■ DisplayPort (2.7 Gbps) ■ Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps) ■ OBSAI (up to 3.072 Gbps) ■ Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Features February 2013 Altera Corporation ...

Page 3

... Note to Table 1–1: (1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. February 2013 Altera Corporation 15,408 22,320 28,848 414 ...

Page 4

... Device Resources 73,920 109,424 149,760 4,158 5,490 6,480 198 280 360 (4) (4) ( (5) (5) ( 3.125 3.125 3.125 (8) (8) ( 310 475 475 Clock Networks and PLLs in February 2013 Altera Corporation ...

Page 5

Package Matrix Table 1–3 lists Cyclone IV E device package offerings. Table 1–3. Package Offerings for the Cyclone IV E Device Family Package E144 M164 Size (mm) 22 × × 8 Pitch (mm) 0.5 0.5 Device EP4CE6 91 ...

Page 6

Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts. Table 1–4. Package Offerings for the Cyclone IV GX Device Family Package N148 F169 Size (mm) 11 × × 14 Pitch (mm) 0.5 1.0 ...

Page 7

... EP4CE115 — — Notes to Table 1–6: (1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage. (2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage. February 2013 Altera Corporation F169 F324 F484 — — C6, C7, C8, I7 — ...

Page 8

... Chapter 1: Cyclone IV FPGA Device Family Overview Table 1–7. Mode ×1, ×2, ×4, ×8/9, ×16/18, and ×32/36 ×1, ×2, ×4, ×8/9, and ×16/18 Logic Elements and Logic Array Blocks in Cyclone IV Devices, and Embedded Multipliers in Cyclone IV Cyclone IV Device Family Architecture Data Width Configurations February 2013 Altera Corporation ...

Page 9

... PHY IP and you can use it in conjunction with your own custom memory controller or an Altera-provided memory controller. Cyclone IV devices support the use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces. February 2013 Altera Corporation I/O Standard LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X ...

Page 10

... Chapter 1: Cyclone IV FPGA Device Family Overview External Memory Interfaces in Cyclone IV Devices Supported Configuration Scheme AS, PS, JTAG, and FPP AS, AP, PS, FPP, and JTAG JTAG Boundary-Scan Testing for Cyclone IV Devices Configuration and Remote System Upgrades in chapter. chapter. Cyclone IV Device Family Architecture (1) SEU Mitigation in February 2013 Altera Corporation ...

Page 11

... This pre-verified hard IP block reduces risk, design time, timing closure, and verification. You can configure the block with the Quartus II software’s PCI Express Compiler, which guides you through the process step by step. f For more information, refer to the February 2013 Altera Corporation Transmitter Channel PCS TX Phase Compensation Byte Serializer ...

Page 12

... Speed Grade 6 (fastest 0° 85° -40° 100° -40° 125° -40° 125° Optional Suffix Indicates specific device options or shipment method N : Lead-free packaging ES : Engineering sample L : Low-voltage device February 2013 Altera Corporation ...

Page 13

... October 2012 1.6 November 2011 1.5 December 2010 1.4 July 2010 1.3 March 2010 1.2 February 2010 1.1 November 2009 1.0 February 2013 Altera Corporation Changes Updated Table 1–3, Table 1–6 and Figure 1–3 packages. Updated Table 1–3 and Table 1–4. Updated “Cyclone IV Device Family Features” section. ...

Page 14

... Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Document Revision History February 2013 Altera Corporation ...

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