GTL16612DL,518 NXP Semiconductors, GTL16612DL,518 Datasheet - Page 2

• Manufacturer Part Number: GTL16612DL,518
• Description: IC TXRX UNVRSL 18BIT 3ST SSOP56
• Manufacturer: NXP Semiconductors

Specifications of GTL16612DL,518

• Logic Function: Translator, Bidirectional, 3-State
• Number Of Bits: 18
• Input Type: GTL
• Output Type: LVTTL, TTL
• Number Of Channels: 18
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 4.9ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SSOP
• Supply Voltage: 3 V ~ 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Other names: 935264022518; GTL16612DL-T; GTL16612DL-T

Philips Semiconductors
FEATURES
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QUICK REFERENCE DATA
ORDERING INFORMATION
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
56-Pin Plastic SSOP
56-Pin Plastic TSSOP
2002 Dec 13
SYMBOL
18-bit bidirectional bus interface
Translates between GTL/GTL+ logic levels (B ports) and
LVTTL/TTL logic levels (A ports)
5 V I/O tolerant on the LVTTL/TTL side (A ports)
No bus current loading when LVTTL/TTL output is tied to 5 V bus
3-State buffers
Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL/GTL+ side (B ports)
TTL input levels on control pins
Power-up reset
Power-up 3-State
Positive edge triggered clock inputs
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
18-bit GTL/GTL
universal translator (3-State)
t
t
I
C
C
PLH
PHL
CCZ
I/O
IN
Propagation delay
An to Bn or Bn to An
Input capacitance (Control pins)
I/O pin capacitance
Total supply current
PACKAGES
PARAMETER
+
to LVTTL/TTL bidirectional
TEMPERATURE RANGE
-40 to +85 °C
-40 to +85 °C
C
V
Outputs disabled; V
Outputs disabled
I
L
= 0 V or V
= 50 pF
2
CC
CONDITIONS
CONDITIONS
T
amb
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for
V
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
CC
= 25 °C
operation at 3.3 V with I/O compatibility up to 5 V.
I/O
= 0 V or V
GTL16612DGG
ORDER CODE
GTL16612DL
CC
TYPICAL
3.3 V
1.9
12
4
8
Product specification
GTL16612
DWG NUMBER
SOT371-1
SOT364-1
UNIT
mA
pF
pF
ns