W3150A+ WIZnet, W3150A+ Datasheet - Page 23

• Manufacturer Part Number: W3150A+
• Description: Ethernet ICs ENET CONTR TCP/IP+MAC
• Manufacturer: WIZnet

Specifications of W3150A+

• Rohs: yes
• Product: Ethernet Transceivers
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 80 C
• Package / Case: LQFP-64
• Ethernet Connection Type: 10Base-T, 100Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IMR (Interrupt Mask Register) [R/W] [0x0016] [0x00]
The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the
Interrupt Register (IR). If an interrupt mask bit is set, an interrupt will be issued whenever the
corresponding bit in the IR is set. If any bit in the IMR is set as ‘0’, an interrupt will not occur though the
bit in the IR is set.
RTR (Retry Time-value Register) [R/W] [0x0017 – 0x0018] [0x07D0]
This register sets the period of timeout. Value 1 means 100us. The initial value is 2000(0x07D0). That will
be set as 200ms.
Ex) For 400ms configuration, set as 4000(0x0FA0)
Re-transmission will occur if there is no response from the remote peer to the commands of CONNECT,
DISCON, CLOSE, SEND, SEND_MAC and SEND_KEEP, or the response is delayed.
Bit
0
7
6
5
4
3
2
1
0
IM_IR7
7
Reserved
Symbol
S0_INT
IM_IR7
IM_IR6
IM_IR5
IM_IR3
IM_IR2
IM_IR1
IM_IR0
0x0017
0x0F
IM_IR6
6
Occurrence of Socket 0 Socket Interrupt
It is set in case that interrupt occurs at the socket 0. For more detailed information of
socket interrupt, refer to “Socket 0 Interrupt Register (S0_IR). This bit will be
automatically cleared when S0_IR is cleared to 0x00.
IP Conflict Enable
Destination unreachable Enable
PPPoE Close Enable
It should be set as ‘0’
Occurrence of Socket 3 Socket Interrupt Enable
Occurrence of Socket 2 Socket Interrupt Enable
Occurrence of Socket 1 Socket Interrupt Enable
Occurrence of Socket 0 Socket Interrupt Enable
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IM_IR5
5
0x0018
0xA0
Reserved
4
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IM_IR3
Description
3
IM_IR2
2
IM_IR1
1
IM_IR0
0