74AUP1G126GN,132 NXP Semiconductors, 74AUP1G126GN,132 Datasheet

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74AUP1G126GN,132

Manufacturer Part Number
74AUP1G126GN,132
Description
Buffers & Line Drivers 3.6 V XSON6
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AUP1G126GN,132

Rohs
yes
Polarity
Non-Inverting
Supply Voltage - Max
3.6 V
Supply Voltage - Min
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
XSON-6
Factory Pack Quantity
5000
1. General description
2. Features and benefits
The 74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE). A LOW level at pin OE
causes the output to assume a high-impedance OFF-state. This device has the
input-disable feature, which allows floating input signals. The inputs are disabled when the
output enable input OE is LOW.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
static and dynamic power consumption across the entire V
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
74AUP1G126
Low-power buffer/line driver; 3-state
Rev. 5 — 28 June 2012
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
Input-disable feature allows floating input conditions
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial power-down mode operation
CC
range from 0.8 V to 3.6 V. This device ensures a very low
CC
= 0.9 A (maximum)
CC
CC
range from 0.8 V to 3.6 V.
Product data sheet
OFF
. The I
OFF

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74AUP1G126GN,132 Summary of contents

Page 1

Low-power buffer/line driver; 3-state Rev. 5 — 28 June 2012 1. General description The 74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A LOW level at ...

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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74AUP1G126GW 40 C to +125 C 74AUP1G126GM 40 C to +125 C 74AUP1G126GF 40 C to +125 C 74AUP1G126GN 40 C to +125 C 74AUP1G126GS 40 C to +125 C 74AUP1G126GX 4 ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1G126 GND 3 001aab653 Fig 4. Pin configuration SOT353-1 74AUP1G126 GND 3 Transparent top view Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Pin description Symbol Pin TSSOP5 and X2SON5 XSON6 GND ...

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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level Don’t care high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 25 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current ...

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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current CC C input capacitance I C output capacitance O = 40 C to +85 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage ...

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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional power-off OFF leakage current I supply current CC I additional supply current CC = 40 C to +125 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage ...

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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional power-off OFF leakage current I supply current CC I additional supply current CC  0.6 V, other input at V [1] One input [2] To show I remains very low when the input-disable feature is enabled. ...

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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter = 25  amb L t propagation delay pd t enable time en t disable time dis = 25  amb L t propagation delay pd t enable time ...

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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t disable time dis = 25  amb L t propagation delay pd t enable time en t disable time dis 74AUP1G126 Product data sheet …continued Figure 10 Conditions ...

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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter = 25 C T amb C power dissipation capacitance MHz [1] All typical values are measured at nominal V [ the same as t and PLH PHL [ the same as t and t ...

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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t disable time dis propagation delay pd t enable time en t disable time dis propagation delay pd t enable time en 74AUP1G126 Product data sheet … ...

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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t disable time dis propagation delay pd t enable time en t disable time dis [ the same as t and PLH PHL [ the same as t and t ...

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... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and Fig 8. The data input (A) to output (Y) propagation delays Table 10. Measurement points Supply voltage Output 0.5  input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH ...

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... NXP Semiconductors Table 11. Measurement points Supply voltage Input 0.5  1.6 V 0.5  2.7 V 0.5  3.6 V Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z ...

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... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE ...

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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.5 0.04 0.25 1.50 mm nom 0.20 1.45 min 0.17 1.40 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version ...

Page 18

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13. Package outline SOT891 (XSON6) ...

Page 19

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1115 Fig 14. Package outline SOT1115 (XSON6) ...

Page 20

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1202 Fig 15. Package outline SOT1202 (XSON6) ...

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... NXP Semiconductors X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0 terminal 1 index area e 1 terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.128 0.85 mm nom 0.80 min 0.040 0.75 Note 1. Dimension A is including plating thickness. 2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 14. Revision history Document ID Release date 74AUP1G126 v.5 20120628 • Modifications: Added type number 74AUP1G126GX (SOT1226) • ...

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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Package outline ...

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